Future ICs Go Vertical

For decades, semiconductor manufacturers have been shrinking transistor size in ICs to achieve the yearly increases in speed and performance described by Moore's Law — chip performance will double every ~18 months. Moore's Law exists only because the RC delay has been negligible in comparison with signal propagation delay. For submicron technology, however, RC delay becomes a dominant factor. It was hoped that change to copper metallurgy, low-k dielectrics and chemical mechanical polishing (CMP) would lower the RC delay and allow the performance increases predicted by device scaling and Moore's Law to continue through this decade.

While copper and CMP have integrated smoothly into the IC fabrication process, the same cannot be said for spin-on or CVD low-k dielectrics. To lower the permittivity and thus the line capacitance, IC manufacturers were forced to resort to materials with no prior history in chip production. The semiconductor industry has postponed three times (three nodes) the transition to true low-k (k<2.8) ILDs, with reliability and yield problems being the major suspects for the implementation delays.

This inability to smoothly integrate low-k has generated many discussions concerning the end of device scaling as we know it, and has hastened the search for solutions beyond the perceived limits of current 2-D silicon devices.¹

One emerging solution is 3-D integration.² If a large number of the long interconnects needed in 2-D structures could be replaced by short vertical interconnects, this would greatly enhance performance. While silicon real estate is consumed by the vertical interconnect, a significant inter-wafer interconnect density can be achieved with a minimal area penalty. 3-D wafer stacking would allow specific functions (i.e., embedded processors, DSPs, SRAM, DRAM, embedded wireless networks, etc.) to be vertically interconnected to create a product. This concept allows for the integration of otherwise incompatible technologies, and offers significant advantages in performance, functionality and form factor. 3-D integration, also referred to as "chip stacking," can be categorized as a system-in-a-package (SiP) solution, where SiP is defined as "any combination of semiconductors, passives, and interconnects integrated into a single package." This is depicted in Figure 1 .

1. 3-D integration allows a large number of the long interconnects needed in 2-D structures to be replaced by a short vertical interconnect that greatly enhances performance.

In March 2004, International SEMATECH's Interconnect Division (Austin, Texas) proposed that they examine 3-D interconnect with through-wafer vias. Announcing that "the complexity and return on R&D investment dollars to get such low-k interconnect schemes to work at advanced technology nodes may prove problematic...and has dampened chipmakers' enthusiasm for the development of ultralow-k materials." SEMATECH envisions the 3-D wafer-stacking technology as "filling the gap between current CMOS technology and more exotic technologies such as carbon nanotubes."

The initial forays into 3-D have involved package stacking or chip stacking in a single package, both of which create interchip interconnects by wire bonding. Stacked chip-scale packages (CSPs) have been in production since 1998, with the vast majority of products-to-date being two-chip memory stacks, such as SRAM plus SRAM, SRAM plus flash, or DRAM plus flash. A thinned, stacked, multichip package is shown in Figure 2 .

2. Initial implementations of 3-D integration have involved package stacking or chip stacking in a single package, both of which create interchip interconnects by wire bonding. A thinned, stacked, multichip package is shown. (Source: Amkor)

Yet, another method was devised by Irvine sensors,³ and others where chips are stacked and connections are established over the edge of the die. In the Irvine process, gold reroute metallization is added to bring all signals to the same edge, and the wafer is diced. The die are stacked, and the stack is lapped in the street area, exposing the ends of the reroute metal. Bus metallization is deposited to the side of the stack, interconnecting the die, which allows signals into and out of the stack. This process is limited, in that all die must be the same size, limiting the stack to a single-die type, and frequent die shrinks require substantial retooling. To alleviate these issues, a newer technology, known as "neo-stack"⁴ has been developed to address these limitations.

So-called "chip-in-polymer" processes have also been developed by IMEC (Leuven, Belgium),⁵ Fraunhofer-Berlin⁶ and Fujitsu (Frankfurt, Germany), among others. In such technologies, chips are thinned, embedded and interconnected in a thin-film/polymer matrix, such as that shown in Figure 3 .

3. Chip-in-polymer processes, such as that shown, have been developed by IMEC, Fraunhofer-Berlin and Fujitsu, among others. In such technologies, chips are thinned, embedded and interconnected in a thin-film/polymer matrix.

Although a significant advantage over single-chip packaging and subsequent interconnection, none of these solutions can achieve the miniaturization or performance achieved by direct die/wafer stacking with vertical connection through the silicon.

Key enabling technologies for building 3-D technology include:

• Through silicon vias — Electrically isolated interconnections through the silicon, which requires deep reactive ion etching (DRIE) to create through vias, dielectric isolation in the interconnect vias, and copper metallization seed and plating.
• Thinning of wafers, usually below 50 µm, by a combination of lapping, DRIE and CMP.
• Precision alignment of wafer-to-wafer or chip-to-wafer.
• Wafer-to-wafer bonding by silicon fusion, polymer bonding, direct copper-to-copper or copper-tin eutectic bonding.

Many of these technologies were originally developed for MEMS technology, and are now finding their application in 3-D integration.

Wafer-to-wafer stacking is most practical for high-die-yielding individual wafer layers. Die-to-wafer bonding, where known good die (KGD) can be selected and bonded to KGD on the base wafer, is best suited for lower-yielding wafer layers.

The breakthrough for silicon through via technology came in 1996 from the MEMS community, with the patenting of what has become known as the "Bosch Process." This process uses SF₆ to rapidly etch the silicon and C₄F₈ to passivate the sidewalls of the via during this multi-step anisotropic etch. This process etches with high selectivity, and achieves extremely vertical sidewalls.

The deep vias are first lined with insulator, and subsequently metallized with TiN/Cu or tungsten (W). In general, SiO₂ insulator is deposited by CVD of TEOS at 300°C. A TiN or TaN adhesion/ barrier layer is then deposited, followed by a seed layer of copper. The best conformal coatings in deep vias appear to be achieved by MOCVD of organometalic precursors, such as tetrakis-ethylmethyl-amido titanium for TiN and (hfac)Cu(DMB) for copper.⁸

Prior to thinning, the wafer is temporarily affixed to a carrier facedown while the backside is ground and polished. The carrier is subsequently released by various techniques.

Several groups have studied the impact of wafer thinning on the electrical characteristics of circuits and have concluded that under normal low-power dissipation levels, thinning has no noticeable impact on the fundamental performance of the devices.^9,10

A major limitation of the 3-D technology is alignment (best case now ±1-2 µm), which currently limits this technology to global interconnect.

Several methods are available for wafer bonding, including:

Silicon fusion bonding — Silicon fusion bonding uses temperature and pressure to join atomically flat oxidized silicon wafers. General requirements for direct wafer fusion bonding include smoothness (microscopic); flatness (macroscopic) — RMS roughness of <1.0 nm; cleanliness; and surface chemistry. Plasma surface treatment can be used to reduce annealing temperatures from ~1000°C down to 200-300°C.

Polymer adhesive bonding — Adhesive bonding, with polymers such as BCB, is less sensitive to interlayer particles affecting bond yield, and does not have the stringent flatness requirements of fusion bonding.¹²

Metal-to-metal and eutectic bonding — Direct copper bonding involves direct copper-to-copper contact at ~400°C. Flatness and roughness requirements are similar to silicon fusion bonding. Small voids are often present because of air entrapment during the bonding, so most practitioners use a cap of tin or gold that forms a eutectic at lower (250°C) temperatures.

Eutectic bonds use an intermediate bonding material that forms a eutectic alloy, such as CuSn. Solid-liquid mixing occurs at temperatures slightly above the eutectic point, and a hermetic solid seal forms upon cooling.

Several universities, research institutes and startups have described 3-D process flows. Although all major IC houses are reportedly studying 3-D integration in-house, far less is known about the details of their commercialization plans. The Table compares several of these processes. Unique details are then discussed.

In the RPI process, BCB (Cyclotene from Dow Chemical, Midland, Mich.) is used for the wafer-to-wafer bonding. The first two wafers are bonded face-to-face, so that the grinding is done on the final stack, not on a handle wafer that requires further transfer. Subsequent layers are added head-to-tail. Devices were tested in liquid-to-liquid thermal shock (-50 to 125°C) and autoclave tests (120°C, 4 hr).

In the Fraunhofer-Munich¹⁴ process (Fig. 4 ), top-side interconnect and pads are created with copper in a deposited TEOS layer. The vias are etched, and the wafer is attached to a handle. After lap and CMP to expose the vias, the wafer backside is isolated, and circuits and pads are formed. The wafer is released from the handle, and the die are diced. The KGD are then remounted on a handle wafer and transferred, all at once, under pressure to the bottom wafer. This allows reflow of all the chips at once. Once the eutectic bond is made, no further processing need occur on the top chip, thus eliminating exposure issues on the now non-planar surface.

4. In the Fraunhofer-Munich process, KGD are remounted on a handle wafer and transferred all at once under pressure to the bottom wafer. This allows reflow of all the chips at once. When the eutectic bond is made, no further processing need occur on the top chip, thus eliminating exposure issues on the now non-planar surface.

5. Japan’s A SET consortium has developed a technology around conventional, available wafers that requires that all thru vias be in the open areas around the peripheral I/O pads. A typical via is shown. (Source: ASET)

ASET (Association of Super Advanced Electronic Technologies), through a METI-sponsored program in Japan started in 1999, has involved researchers from 18 companies. The consortium has developed a technology around conventional, available wafers, which requires that all through vias be in the open areas around the peripheral I/O pads.¹⁵ 10 µm vias are etched through the silicon and isolated with SiO₂. A barrier layer of TiN and a seed layer of copper are deposited by CVD, and the vias are then plated up with copper. A cross-section of the vias is shown in Figure 5 . As a final pre-commercial test, the process was successfully applied to commercially available CCD wafers.

Tohoku University (Japan), in conjunction with Mitsubishi Heavy Industries (Shinagawa, Japan) and Fuji-Xerox, developed technology for 3-D ICs for very fast image processing for robotic applications.¹⁶ In the 3-D stackup, the 2-D image signals are simultaneously transferred in the vertical direction and processed in parallel in each layer.

In their process, 2 × 2 × 30 µm vias are etched in the wafers, oxidized for isolation and filled with n+ polysilicon or tungsten to form the buried interconnect. The wafers with buried interconnections is glued to a carrier wafer and thinned down to ~30 µm by grinding and CMP. The thinned wafer is bonded to a silicon base wafer through 5 µm In/Au evaporated microbumps.

Lincoln Labs,¹⁷ MIT (Lexington, Mass.) and IBM have developed similar processes for silicon-on-insulator (SOI) wafers. MIT has mainly studied the wafer bonding and device transfer processes. Wafer bonding is achieved by direct copper-to-copper bonding.¹⁸ In the described IBM process, full wafers of devices fabricated on SOI are bonded to a glass "handle wafer." The silicon wafer is then backside-ground and etched back to the embedded oxide layer. Fusion bonding (&lt;300°C) is used to transfer the thinned wafer on the handle to the base substrate wafer. The glass handle is then released by laser ablation of the adhesive polymer, and interlevel vias are formed after layer-stacking by the dual-damascene process.¹⁹

Toshiba (New York, N.Y.) has described a process for stacking flash memories using standard 3-D processing. It was found that the chips operated normally after via formation, thinning and backside processing.²⁰ Infineon (Dresden, Germany) is the first to announce that they are moving to production in 2005 with a two-chip face-to-face structure developed jointly with Fraunhofer-Munich. Their process involves chip-on-wafer stacking, as shown in Figure 6 .

6. Infineon put this process — two-chip face-to-face wafer stacking — into production this year. (Source: Infineon)

MCNC-RDI, which has spun out several commercial operations such as Unitive (bumping and assembly) and Cronos (MEMS), has been working behind the scenes on several government and corporate programs involving 3-D integration.

7. MCNC has achieved 99%+ interconnect operability with this type of two-layer silicon stack in a 256 × 256 array of 3-D interconnects.

In the DARPA VISA (vertically interconnected sensor array) program,² we have developed (in collaboration with DRS Infrared Technologies in Dallas) a low-temperature process compatible with the presence of high-resolution, infrared, focal plane arrays. The VISA device architecture allows additional signal processing, resulting in performance gains necessary for next-generation strategic and tactical infrared sensor systems. Figure 7 shows a SEM micrograph of a cross-section of a two-layer silicon stack incorporating a 256 × 256 array of 3-D interconnects. We have achieved 99.9%+ interconnect operability on such devices. Vias, currently in the 4 µm range, are insulated with a proprietary conformal polymer and then filled by a low-temperature copper process. After thinning, die are joined by a low-temperature polymer adhesion process.

Ziptronix (Research Triangle Park, N.C.) uses a patented ZiROC process to do silicon fusion bonding of highly planarized oxide surfaces at room temperature. They have announced that they expect to ship their first 3-D silicon in the first half of 2005. They are targeting the mixed-signal market by combining digital and analog devices built on different substrates.

Tezzaron (Naperville, Ill.) noted that their FaStack memory uses a combination of "our own IP, licensed stacking technology and wafer bonding technology co-developed with IME." They claim to be readying for volume production ramp in 1Q05 with 1-4Gb DDR2 memory delivery later in 2005.²²

So where does 3-D technology stand today? Remaining 3-D technology issues include:

• CAD tools for 3-D design, which are not widely available and not understood by a majority of design engineers.
• Thermal dissipation of heat from the stack.
• Yield that is exacerbated in wafer-to-wafer, stacking the need for common die size wafer-to-wafer alignment limitations, which has not yet achieved ±1 µm.
• Thermal-mechanical stresses induced by the post-device processing.

Some of the things needed for this technology to take off include:

• Pervasive CAD tool that is accepted by the chip design community.
• Demonstration of high-volume product — the first step in this regard would be success of the Infineon or Tezzaron products in 2005.
• Agreed-upon generic solutions to the thermal and mechanical issues.
• Yield and cost determination based on real products.
• Clearly demonstrable performance improvements.