Rohm and Haas, IBM Tackle Implant-Level Lithography Materials
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 2/25/2008 5:45:00 AM
Rohm and Haas Electronic Materials has entered into a joint development agreement (JDA) with IBM to develop patterning materials and processes to enable implant at and below the 32 nm node.
Ion implantation has become a critical process within transistor fabrication, selectively introducing electrical charges into extremely small areas that have been defined by preceding lithographic steps. At 32 nm and below, however, lithography at the implant levels becomes difficult for several reasons, chief among them being reflectivity control.
Substrate reflectivity variations require creative reflectivity control techniques, noted Rao Varanasi, a senior technical staff member at IBM Microelectronics, and manager of lithography materials R&D. “The other challenge is, obviously, resolution and profiles on a variety of film stacks and topography, and adhesion on a wide variety of substrates. And another important thing is wet etch performance and different etch chemistries,” he said. “But the most important thing is reflectivity control. And that really requires the creative solutions.”
The need to control reflectivity was a key element that was identified by both IBM and Rohm and Haas early on when they first began discussions, according to Rick Hemond, worldwide marketing director for Microelectronic Technologies at Rohm and Haas Electronic Materials. Some of the standard ways to control reflectivity are with either bottom antireflective coatings (BARCs) between the resist and the substrate or top antireflective coatings (TARCs). But you can’t use traditional BARCs, Hemond said, because of the implant process.
What makes BARCs particularly tricky for use on implant layers, Hemond explained, is the underlying topography, which is actually changing during the implant process. “The substrates are changing as well as the step heights are changing,” he said. “So you have to be careful that the BARC doesn’t pool up or thicken in particular areas, or get too thin over these edges of steps. So the way that the BARC actually flows and then sets up is a challenge on the implant area.”
Although Rohm and Haas has dealt with this challenge on other layers as well, it is particularly challenging for the implant layers, especially as the devices scale down to smaller geometries. Where this really becomes an issue is at the 32 nm node, according to Hemond. “At 45 nm, the vast majority of customers use 248 single-resist solutions – some of them with a TARC on top, some of them without a TARC, depending on the customer design. So at 32 is really the crossover point where you need to get a bit more creative in the solutions that you bring to this.”
At 32 nm, the number of implant levels is also growing, increasing the number of levels that have to be handled. It is anticipated that ~40% of photo levels in advanced logic designs will be implant.
“Also, we have a competing pathway between 248 implants and 193 implants,” Varanasi added. “So constantly, we need to make decisions and optimize materials properties for both wavelengths. And until the 32 nm node, everything was centered around only 248 implants. So that increases complexity.”
The two companies signed the JDA in mid-December last year, and are just getting underway with meetings to decide what areas to attack first and who will do what, according to Jim Fahey, president of Microelectronic Technologies for Rohm and Haas Electronic Materials.
The two companies are looking at all sorts of materials opportunities at this point, according to Hemond. “We’ve just begun this JDA, and we’ve brainstormed some different ideas, but we haven’t chosen a particular materials pathway yet,” he said.
“There are a lot of ideas and a lot of IP associated with those ideas, and we’re going to take a look at all of them collectively and figure out what is the best option for a given technology challenge,” Varanasi added.
Work on the joint collaboration will take place at IBM’s East Fishkill, Yorktown and Albany facilities, and at Rohm and Haas Electronic Materials’ Advanced Technology Center in Marlborough, Mass.
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