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RSS   Wafer Processing

The latest news and information on major semiconductor manufacturing process steps, including etch, deposition, epitaxy, chemical mechanical planarization (CMP) and thermal processing.

  • TSMC Begins Production of 40 nm Designs
    David Lammers, News Editor - 11/17/2008
     TSMC said it is now in production of 40 nm designs for a wide variety of customers, ranging from Altera to Sun Microsystems. Although Qualcomm and others have used a TSMC 45 nm process, TSMC Vice President Di Ma said the company developed an IP platform and design support ecosystem for the 40 nm design rules. More

  • IBM Offers 45 nm SOI Foundry Solution
    David Lammers, News Editor - 11/10/2008
     IBM is offering a 45 nm SOI foundry solution to customers seeking to reduce active power consumption. ARM developed an SOI standard cell library, in conjunction with SOI wafer vendor Soitec, that eases SOI designs. Chartered will provide a second-source foundry capability for high-volume SOI customers. More
  • Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
    Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif. - 11/01/2008
     Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes. More
  • Resistivity Reduction Enables Tungsten Scaling
    Frank Huang, Anand Chandrashekar and Michal Danek, Novellus Systems Inc., San Jose - 11/01/2008
     As features shrink beyond 32 nm, conventional pulsed nucleation layer (PNL) will not provide the necessary resistivity performance. Tungsten nucleation and CVD fill developments can extend ALD tungsten to 2X nm features and provide needed resistivity. More
  • SMIC, UMC cut capexs
    By Suzanne Deffree, Managing Editor, News - 10/29/2008
     Amid losses and poor visibility, the two foundries separately announce capex reductions while reporting on Q3 numbers. More
  • Logic Technologies Face Off at IEDM
    David Lammers, News Editor - 10/28/2008
     At the International Electron Devices Meeting (IEDM) planned for Dec. 15-17 in San Francisco, IBM and its partners AMD and Freescale will present a thin SOI technology used to create a 22 nm functional SRAM with a cell size of 0.1 µm2. Intel researchers will detail their 32 nm logic platform, which delivers drive currents of 1.55 mA/µm for the NMOS and 1.21 mA/µm for the PMOS transistors. More
  • ISMI Outlines 450 mm Wafer, NGF Roadmaps
    David Lammers, News Editor - 10/27/2008
     ISMI managers described progress at the 450 mm wafer Interoperability Test Bed, and described the Phase 2 roadmap at last week’s ISMI Symposium on Manufacturing Effectiveness. Also, the Next Generation Factory program at ISMI is continuing work on cycle time improvements for existing and greenfield 300 mm wafer fabs, including support for 12-wafer lots. More
  • IMEC Calls EUV Performance ‘Impressive’
    Laura Peters, Editor-in-Chief - 10/23/2008
     After only five months’ experience with a new source on its Alpha Demo Tool (ADT), Kurt Ronse, director of the Advanced Lithography Program at IMEC (Leuven, Belgium), said he is impressed with the extreme ultraviolet (EUV) tool’s stability and performance to date. IMEC has demonstrated the ability to resolve 35 nm flash patterns with the scanner. More
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    Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif., 11/01/2008
 Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes....

    Resistivity Reduction Enables Tungsten Scaling
Frank Huang, Anand Chandrashekar and Michal Danek, Novellus Systems Inc., San Jose, 11/01/2008
 As features shrink beyond 32 nm, conventional pulsed nucleation layer (PNL) will not provide the necessary resistivity performance. Tungsten nucleation and CVD fill developments can extend ALD tungsten to 2X nm features and provide needed resistivity....

    Yale’s T.P. Ma Proposes Unipolar CMOS
David Lammers, News Editor, 10/08/2008
 Professor T.P Ma of Yale University has proposed a new type of CMOS, named Unipolar CMOS, that would use electrons in both channels. “All I am doing,” Ma said, “is replacing the conventional p-channel by an n-channel transistor that has a negative threshold voltage.” Ma, who won the IEEE Andrew Grove award in 2005, said Unipolar CMOS would gain a speed advantage by not using the slower holes as carriers. Density would improve by using a shared contact....

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