Pellerin Peers Down AMD Process Options

David Lammers, News Editor -- Semiconductor International, 12/18/2007 7:51:00 AM

John Pellerin, director of logic technology development at Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.), is sitting in one of the industry’s hot seats now, as the company seeks to get back on track with the design and manufacturing synergies that served it so well in 2006.

With 2007 — arguably an annus horribilus for AMD — nearly behind it, Pellerin said AMD is “ramping aggressively” toward 2008 45 nm production at its Fab 36 in Dresden, Germany.

During an interview held during the International Electron Devices Meeting (IEDM) in Washington, D.C.,  Pellerin said the AMD/IBM/Sony/Toshiba alliance at Fishkill, N.Y., has “set a high bar for introducing high-k and metal gate technology, in terms of getting the scaling benefits out of it at the outset. With our high-k implementation, we have a very transparent design. We can take the designs based on poly [gates] and map them over seamlessly to a high-k/metal gate solution.”

AMD plans high-k/metal gate technology for 45 and/or 32 nm technology generations.

AMD prides itself on being able to make quick adjustments to its process recipe, based on its automated precision manufacturing (APM) technology. That would allow high-k/metal gate to enter the 45 nm process flow more easily, Pellerin said. For the SPICE models given to its design teams, and from a physical design perspective, high-k/metal gate involves “minor electrical changes.”

AMD is currently making prototype 45 nm products based on high-k/metal gate technology “to assess the value to customers,” he said. The high-k/metal gate designs “drop in quite seamlessly to our overall process flow. AMD has not communicated its exact high-k/metal gate roadmap, but we are moving in the right direction,” he said.

The elimination of poly depletion is an important aspect of high-k/metal gate technology. With high-k/metal gate, AMD is targeting an inversion thickness of 10-14 Å, “which we have not been able to get to with oxynitrides and poly gates. There, the T_inv has been limited to 18.5 Å.

The thinner T_inv from high-k/metal gate technology “immediately translates into gate-length scaling, easily giving us a 5 nm improvement. Since the 90 nm generation, we have been holding gate length fairly constant, so as we go to 32, we should get the conventional shrinking of the gate length. That will make density scaling much easier as well,” he said.

Overall, AMD expects to achieve a 20% performance improvement at the 45 nm generation from strained silicon and ultralow-k dielectrics, with high-k/metal gate providing the ability for further enhancements.

Silicon carbon strains nFETs

Pointing to rapid improvements in pFET performance because of embedded silicon germanium (eSiGe), where strain has roughly tripled pFET mobilities, the attention now is how to take advantage of the improved ratio between the nFETs and pFETs. “We need to revisit the way circuits are optimized,” Pellerin said.

AMD engineer Bin (Frank) Yang and other AMD authors published work on using silicon carbon (SiC) as a means of boosting strain in the nFETs. Their IEDM paper was entitled, “(110) Channel, SiON Gate-Dielectric PMOS With Record High I_on=1 mA/µm Through Channel Stress and Source Drain External Resistance (Rext) Engineering.”

Pellerin said there is a good chance that SiC “will come into its own,” perhaps as soon as the 32 nm generation. The smaller carbon atoms create a tensile, or stretching, stress on the silicon lattice, aiding electron mobility.

With germanium concentrations approaching 30% in the pFETs, the concentration of carbon in the nFET embedded source and drain regions is only ~2%.

Keeping the carbon atoms in place is the major challenge. “There have been good advances in terms of the ability to substitute carbon [in the silicon lattice]. There has been a great deal of learning there, and I think it will come into fruition.”

Analysts — and AMD’s own technical managers — have debated the cost/performance benefits of silicon on insulator (SOI) technology as scaling proceeds. SOI wafers themselves add several hundred dollars in costs. However, Pellerin said SOI’s critics tend to overlook SOI’s added benefits at 32 nm and beyond.

Soft error rates are dramatically better in SOI technology, and isolation is also easier to accomplish. “Isolation in bulk is not without costs. In SOI, isolation doesn’t require building such deep wells,” Pellerin said.

AMD is moving to ultralow-k dielectrics for 45 nm interconnects.

Asked if the thickness of the SOI silicon layer will limit the ability to perform strain engineering on SOI wafers, Pellerin said, “Certainly, we would be confined by the thickness if we stuck with the way we do strain today. But one avenue is raised source drains, putting the SiGe or silicon carbon in a raised source and drain.”

SOI will transition from partially depleted to fully depleted channels at some point, but that will come after the 32 nm generation. “Partially depleted planar is the incumbent at 22 nm. Any option will have to supercede that. Multi-gate finFETs are what we might consider the main option being evaluated at the 22 nm generation, and they would be a fully depleted technology. Fully depleted finFETs is one of the options, but we have not made a decision,” he said.

With interconnect capacitances becoming a rising share of total switching capacitance, Pellerin said the air gap technology pursued by the Fishkill Aliance should be seen as an “extension of our ultralow-k effort to drive down the dielectric values, including at the sidewalls of the metal lines. We want to distribute porosities over the cross-section of the pipe while maintaining the mechanical properties.”  

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

• Topics
• Author

Related Content

 

By This Author

• Despite Losses, Toshiba to Continue Aggressive Investments
• Environmental Regulations Growing More Complex
• Kovio Demonstrates RFID Tags Using Printed Electronics
• Yale’s T.P. Ma Proposes Unipolar CMOS
• AMD and Abu Dhabi Join Forces to Keep Fabs on Track
• » MORE

SPONSORED LINKS

SI Resource Center

Browse Resources by Type:

• White Paper

• Industry Survey of Wafer Fab Reticle Control Quality Strategies
  Ieee Operations Center | White Paper
  VIEW NOW
• Characterization and Optimization of Single Wafer Processing Equipment with Advanced Aqueous Formulations to Achieve Lower Cost of Ownership for Advanced Cu Interconnect Cleaning Processes
  Ieee Operations Center | White Paper
  VIEW NOW
• Interconnect Etch Tool Sensitivity to Wafer Backside Composition and Process Induced Defects
  Ieee Operations Center | White Paper
  VIEW NOW

View More