Intel Takes 45 nm HKMG Process to IEDM
David Lammers, News Editor -- Semiconductor International, 12/14/2007 11:31:00 AM
Intel Corp. (Santa Clara, Calif.) provided some details of its 45 nm high-k/metal gate (HKMG) process flow at the International Electron Devices Meeting (IEDM) in Washington, D.C., although key elements of the pFET electrode metal remained shrouded.
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| Kaizad Mistry, Vice President of Logic Integration, Intel |
The hafnium-based gate dielectric has a 1 nm equivalent oxide thickness (EOT) for both n- and p-type transistors, with a 7 Å interfacial layer, which Mistry referred to as a “transition layer.” Although Intel does not provide its inversion thickness, Mistry said in an interview that the difference between the EOT and Tinv “is about 4 Å, plus or minus 1.” The physical thickness of the HK layer was 18-20 Å, which is thick enough to provide what Mistry said was a 25× improvement in NMOS leakage current, compared with SiO2, and a three orders of magnitude (1000×) improvement in PMOS leakage.
The 35 nm gate length transistor has an nFET drive current of 1.36 mA/µm at 1 V operation, which he said was a 12% improvement over the 65 nm process. By increasing the level of germanium in the embedded silicon germanium (eSiGe) stressors from 17% at the 90 nm generation to 23% at 65 nm to 30% at 45 nm, Intel has boosted pFET performance considerably, with a 3× improvement in hole mobilities. That results in a 1.07 mA/µm drive current for the pFET, which Mistry said is “by far, the highest performing PMOS transistor.” Compared with the 65 nm pFET, the 45 nm pFET is 51% faster.
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| Intel's 45 nm transistor includes a high-k/metal gate (HKMG) stack. |
The stronger pFET is causing Intel’s design teams to consider the mix of NOR gates, which rely on the nFETs, and NAND gates, which are more pFET-dependent. "With a higher beta ratio [between n- and pFET performance] of 1.3, we can tell our designers up front so they can take advantage,” he said.
For a gate with a fanout of two, the switching speed is 5.1 ps.
In a post-session interview, Mistry said the metal gate-last approach produces a better pFET technology than the gate-first approach. “There has never been a high-performance pFET produced with a gate-first approach." The use of a metal gate helps improve threshold voltage (Vt) pinning and gets rid of the poly depletion problem that had robbed performance. With an oxide poly gate stack, “We were running out of atoms,” Mistry said, making the move to HKMG imperative.
In an outline of the process flow, Mistry said after the silicon-germanium stressors are deposited, a dummy poly gate is removed, which aids in the formation of pFET transistor and retains strain in the nFET transistor.
At later conferences, Intel will describe its patterning technology, which includes double patterning steps at one or more of the critical mask levels using dry 193 nm lithography. “We achieved an amazing fidelity despite using dry lithography,” Mistry said.
The mask count for transistor formation was kept the same as the 65 nm process, he said, despite the more complex HKMG deposition, by reducing mask layers “elsewhere in the process.” Intel did add masks for the extra interconnect layer, he said.
Another major innovation that Intel will detail next year is the use of a trench contact with local routing, which eases the burden of creating the circular contact arrays — one of the most challenging lithography steps.
With SRAM arrays dominating the microprocessor silicon real estate, Mistry said Intel was able to double its array density compared with the 65 nm process. The 45 nm process yields 1.9 Mb/mm2, with cell sizes of 0.346 µm2 and 0.382 µm2 for the two SRAM types used. “What matters as much as cell size is how many bits can be packed into a given area including the row and column circuitry,” he said.
To reduce capacitance in the interconnect layers, which now account for a majority of the capacitance, Intel moved to low-k dielectrics for almost all of its interconnect layers. Beneath the copper bump that connects to the lead-free package is a very thick (7 µm) M9 interconnect layer, which Intel calls a redistribution layer (RDL).
Intel is putting increasing emphasis on reducing capacitance in the interconnect layers, as gate capacitance is only about one-fourth of total capacitance, he said. To do that, “At lower layers, we reduced the thickness of the etch-stop layers.” By using a silicon-carbon-nitride etch-stop layer with a k value that is in between SiO2 and SiN, Intel was able to reduce the etch-stop capacitance by 5% for lower layers by cutting the etch stop layer in half, compared to that of the 65 nm generation.
“By January 2006, this process was yielding fully functional test chips. Now, products at Intel’s Fab 32 in Arizona are matching the yields with the same defect densities as our fab in Oregon,” he said.
The major challenge in development of the HKMG technology was determining a combination of metals that could replace polysilicon in the pFET, one that would provide the proper workfunction.
Scott Thompson, a professor at the University of Florida (Gainesville, Fla.), said he believes Intel is using a mixture of well-known metals, including titanium, titanium nitride, aluminum and tantalum nitride. “It is difficult to know for sure what sequence Intel deposits the metals because, during the thermal cycles, they become intermixed. And perhaps the exact metals are not so important as is the fact that Intel used well-known standard metals. What is important is the process control margins, the rate of deposition and polishing. To keep the level of polishing uniform, within a couple of hundred angstroms, over a 12-in. wafer, over all kinds of topographies, that is an impressive accomplishment,” Thompson said.
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