Flash Anneal Must Maintain Interface Control

The latest tool in the process engineer's toolbox, the flash anneal, complements the spike rapid thermal annealing (RTA) methods already used to provide dopant activation while limiting dopant diffusion. However, the flash anneal is even more precise, rising from ~900°C to ~1300°C and back down within milliseconds, limiting diffusion to almost negligible amounts. In addition, the flash anneal is typically not at temperature long enough to transform crystalline films to the amorphous state, so it can play a key role in maintaining channel strain. At the upcoming International Electron Devices Meeting (IEDM), held Dec. 10–12 in Washington, D.C., engineers from a number of companies will present the benefits of incorporating flash annealing techniques.

Pankaj Kalra of the University of California-Berkeley, along with researchers from Intel (Santa Clara, Calif.), Sematech (Austin, Texas), University of Texas at Austin, Advanced Micro Devices (AMD, Sunnyvale, Calif.), IBM (Yorktown Heights, N.Y.) and GIST (Gwangju, Korea), examined the impact of flash annealing on the performance and reliability of high-k and metal gate MOSFETs for the 45 nm node. They were able to achieve <15 nm junctions with sheet resistivity (R_s) in the 1 k Ω/sq range, suitable for the 32 nm node, with less dopant diffusion and better dopant activation using flash annealing.

The group fabricated and tested gate-first CMOS devices with high-k (3 nm HfSiO by atomic layer deposition [ALD]) deposited on 1 nm of SiOx, followed by post-deposition anneal in NH₃. The gate electrode (100 nm TiN by ALD) was deposited, followed by polysilicon low-pressure chemical vapor deposition (LPCVD). Then, shallow extensions were implanted, spacers were formed and the deep source/drain (S/D) ion implants were implanted and activated by either a spike or flash anneal. The flash anneal resulted in improved short-channel effects in the form of lower subthreshold slope (SS) and reduced drain-induced barrier lowering. The HfSiO/SiO_x interface appeared slightly rougher in high-resolution TEM images of the flash annealed samples. For both anneals, well-behaved CV curves were obtained with comparable equivalent oxide thicknesses and flatband voltage for NMOS transistors. Positive bias temperature instability (PBTI) measurements indicated little dependence of trap generation on the annealing procedure. However, the interface (HfSiO/SiO_x) had higher trap density (N_it) in the case of the flash annealed devices, as indicated by charge-pumping measurements. Negative bias temperature instability (NBTI) results also indicated differences (Figure). The researchers surmised that the high-k induced oxygen vacancies within the SiO_x caused by high temperature exposure during flash annealing (~1300°C) could possibly explain the increased N_it. A post-metallization anneal step was added to passivate the damage, which also lowered the SS, indicating improved interface quality.

Poorer characteristics for the flash-annealed gate stack may be attributed to the HfSiON/SiOx interface. (Source: UC Berkeley)

Key to implementing flash annealing is proper positioning among other annealing steps in the process flow. T. Sanuki from Toshiba Corp. (Yokohama, Japan), with researchers from NEC Electronics Co. Ltd. (Shanghai) and Sony Corp. (Tokyo), found that by applying flash annealing prior to spike RTA for S/D anneal, the channel stress in pFETs with embedded silicon germanium (eSiGe) S/D can be enhanced. In the nFET device, the flash anneal recovered the damaged layer in the S/D extension caused by implantation and suppressed transient enhanced diffusion. In a 45 nm process with 34 nm gate length nFET and pFET transistors, they observed that flash annealing provides instantaneous recrystallization and recovery of the implanted S/D damage layer. The recrystallization restrains the strain relaxation in the pFET with eSiGe S/D. Both strain enhancement and low parasitic resistance were realized.

In the nFET, the threshold voltage (V_t) roll-off was also improved by applying flash annealing prior to spike RTA. Flash annealing recovered the damage in the S/D and S/D extensions. In terms of performance, an 11% improvement in pFET saturation drive current (ID_sat) was realized, for a result of to 750 μA/μm with eSiGe S/D. The ID_sat of the nFET was improved by 8% to 1160 μA/μm for I_off of 100 nA/μm at V_dd of 1 V.

When the spike anneal preceded the flash anneal, the performance gain in ID_sat for the pFET was not realized. The researchers determined that the SiGe layer surface turns amorphous by S/D implant and is recrystallized by spike RTA. This recrystallization decreases the stress in the eSiGe layer. When performing flash prior to spike RTA, the stress relaxation does not occur because of instantaneous recrystallization.

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