Trends in Shallow Junction Engineering

Junction scaling has traditionally meant the proportional scaling down of the entire transistor so that with each generation gate widths are narrower, dielectrics thinner, and source/drain (S/D) junctions shallower. At the 45 nm technology node, achieving ultrashallow junctions (USJ) of 150–200 Å for S/D extensions is just one of the key challenges. The other is doing so while keeping parasitic resistance low.

Because the resistance of the S/D extension is related to the concentration of electrically active dopant, charge carrier mobility and junction depth, it therefore follows that for shallower S/D extensions, achieving low enough sheet resistance (R_s) becomes a progressively more challenging task. The inability to reduce and control S/D R_s could ultimately impact device performance, such as drive current. Efforts are well underway to increase the concentration of electrically active dopant, minimize dopant diffusion through ion implantation and annealing schemes, and minimize dopant loss during post-implant photoresist removal and cleaning steps. Alternative doping methods, such as plasma doping and epitaxial processes (Fig. 1), are also being investigated.

1. The epitaxial growth chamber may one day be used to dope S/D junctions, depositing electrically active dopants with no need for subsequent annealing. (Source: Applied Materials)

Ion implantation

Shallow junction implants must be low energy with high beam current, have good angular integrity, uniformity and low particle contamination. Ultrashallow S/D extensions pose the greatest challenge.

Implant parameters consist of the atomic mass of the implanted species, energy, dose and incident angle. A source of ions is created and, through complex electromagnetics, a desired ion species is selected and a beam of ions directed toward a wafer is implanted. The energy of the implant establishes the depth of the dopant. Modern high-current implanters have a high degree of versatility and can generate precise and reproducible ultralow-energy ion beams.

To meet the requirements imposed by advanced devices on USJs, additional precision materials modification implant steps using non-doping species have been developed and implemented. For example, pre-amorphization of silicon by implanting germanium or silicon atoms prior to a doping implant minimizes ion channeling of the dopant and is one of the most common implant steps in use today. Pre-amorphization implants convert the surface layer of silicon from crystalline to amorphous, thereby achieving shallower and more abrupt dopant profiles as well as improving dopant activation during post-implant anneal.

An additional carbon implant is frequently used in high-performance devices. This implant is specifically designed to change the material property of silicon to slow dopant diffusion during subsequent anneal steps. Carbon captures mobile interstitials that are released by end-of-range damage and during post-implant anneal. Once the interstitials are rendered immobile, they are no longer available to interact with the doping boron atoms, which could otherwise result in an elevated level of transient-enhanced diffusion and interfere with electrical activation. In essence, carbon implants allow for shallower junctions and lower junction resistivity.

"A reduced thermal budget for the post-implant anneal makes it difficult to completely anneal out end-of-range crystal damage from pre-amorphizing and other implants," said Yuri Erokhin, senior director of strategic technologies at Varian Semiconductors (Gloucester, Mass.). This residual damage may result in increased defect-related junction leakage in S/D and S/D extensions, and may pose a problem for meeting leakage current targets in low-power devices at sub-32 nm nodes.

New implant species

The necessary low energies needed to limit depth penetration during USJ implants can result in low throughput. One solution developed at Varian uses ionized molecules of carborane as a p-type dopant. "The molecule contains 10 boron atoms, which has made it possible to deliver boron atoms to the substrate at a significantly higher rate, thus improving throughput relative to conventional monomer implants," Erokhin noted. And because it is a helium molecule delivered with a large quantity of boron, excellent beam angular integrity and enhanced silicon amorphization can be achieved. The latter advantage could potentially eliminate the germanium pre-amorphization implant and reduce end-of-range damage. Compared with other molecular species, carborane has higher thermal stability, making it possible to run on a standard Varian high-current implanter, thereby precluding the need to dedicate the implanter to molecular species only, Erokhin stated.

A novel annealing scheme

Technological advances first appear in performance-setting logic devices, followed by DRAM then flash. Therefore, it is not surprising that rapid thermal processing (RTP) is still in transition in flash production lines while newer annealing techniques, such as spike and millisecond anneals, appear in advanced logic. By combining the latest annealing techniques, balancing the trade-off between activation and diffusion may be a thing of the past. It is this ability to separate the diffusion and activation phenomena that provides the control needed stay within the thermal budget required in USJ formation.

A spike anneal is an RTP technique that ramps up and down while remaining at a peak temperature between 950°C to #1100°C in the range of seconds. A millisecond anneal is performed with a flash lamp or laser, and peaks at 1300°C for a duration three orders of magnitude shorter than a spike anneal.

The concept is simple. A spike anneal is performed to create just enough lateral diffusion to connect the S/D to the channel. A millisecond anneal follows at a temperature high enough to produce dopant activation but short enough in duration to prevent diffusion.

Recent studies have shown the effectiveness of flash annealing in some advanced device structures. Sematech (Austin, Texas) initiated a detailed investigation fabricating USJs using millisecond flash annealing and its effects on hafnium-based dielectric and metal gate stacks (Fig. 2). "The flash-annealing process was optimized for 90 Å junction depths, resulting in excellent device performance metrics," said Raj Jammy, director of front-end products at Sematech. "It was found to be compatible with high-k/metal gate stacks, although a hitherto unknown defect mode that reduced mobility was identified for the first time." While the interface in flash-annealed devices was shown to be degraded in comparison with the spike-annealed devices, resulting in mobility loss, a proprietary passivation anneal helped recover mobility loss by improving the quality of the interface. "Overall, the study demonstrated flash annealing to be compatible with advanced gate stacks for CMOS scaling, " Jammy said.

2. A study investigating the impact of flash annealing on high-k/metal gate MOSFETs indicates improved short-channel effects, shallower S/D extensions, Xj and lower Rs. (Source: Sematech)

The efficacy of millisecond anneals were further demonstrated at Advanced Micro Devices (AMD, Sunnyvale, Calif.), where laser- and flash-annealing steps have been successfully integrated into the company's 45 nm production technology. A performance improvement of ~10% could be achieved, said Manfred Horstmann, senior manager of technology and integration engineering at AMD's Fab 36 in Dresden, Germany. The advanced annealing scheme does not cause gate oxide reliability issues within a given power density limit. Above that power level, a strong increase in gate leakage can be observed. And with even higher powers, the gates are physically damaged. "We found the critical power-density level in the range of an equivalent temperature of 1350°C. Below that level, long-term reliability issues were not observed," Horstmann said.

Millisecond anneals are still relatively new and potential problems still exist, such as the possible relaxation of strained cap layers or embedded silicon germanium (SiGe) layers, and dopant deactivation for cap layers deposited at low temperatures, Horstmann noted. In time, these and other thermal matters will be thoroughly investigated.

Clean solutions

The International Technology Roadmap for Semiconductors (ITRS) surface preparation technology roadmap (2006 updates) targets silicon and dopant loss or consumption to be <0.4 Å per cleaning step at the 45 nm technology node and 0.3 Å at 32 nm. With 10–15 clean cycles at the 45 nm node, a loss of only 4 or 5 Å can be tolerated. The losses can occur throughout the fabrication process during wet and dry cleans, photoresist strip and activation anneals following ion implantation.

The amount of substrate loss during an SC-1 wet clean has become a significant factor in degrading device performance at the 45 nm node, said Satoru Muramatsu, process engineering manager of process technology at NEC Electronics Corp. (Kawasaki, Japan). The primary approach of lowering the temperature and concentration of the SC-1 solution can effectively reduce substrate loss; however, the cleaning ability is compromised. Wet cleaning solutions alone are not enough. It has become necessary to integrate optimum process conditions across process steps that consume silicon, such as dry etching, plasma strip and wet cleans. In a broader sense, the critical challenge is one of process integration.

An example of an integrated process developed at NEC Electronics covers the silicon surface with a thin protective coating during a first clean step to minimize loss. In the next step when it is necessary to perform the SC-1 cleaning without the protective film, the best of the wet cleaning conditions to achieve a minimal loss is used. Comparing an integrated process flow with a conventional flow (Table), 30% of the number of steps where S/D dopant loss occurs are eliminated, thus reducing the number of loss steps from six to four.

The effectiveness of integrating processes is clear. Changing chemistries of cleaning solutions and plasmas offers a direct approach to limiting the loss of silicon.

Non-fluorine strip chemistries

Photoresist stripping following high-dose USJ implants requires a high degree of wafer cleanliness, minimum substrate loss and maximum dopant retention, said Keping Han, senior scientist of the cleaning process technology department at Axcelis Technologies (Beverly, Mass.). A resulting silicon recess (silicon loss) under the S/D extensions can change the junction profile, therefore increasing the S/D extension resistance and decreasing drive currents.

Aggressive fluorine-containing chemistries are often used to enhance resist strip and residue removal, therefore ensuring the desired degree of wafer cleanliness. However, at 45 nm and beyond, the accompanied amount of substrate loss is unacceptable, making non-fluorine plasma dry strip chemistries of particular interest. One such process has been developed on the Axcelis RapidStrip 320 system to achieve minimal substrate loss and low defectivity. A silicon loss was held to 3 Å even after a total of 16 resist strip steps (Fig. 3). This is equivalent to a loss of <0.2 Å per clean cycle, which is less than the ITRS loss requirement for the 32 nm node.

3. The graph illustrates the effectiveness of using the non-fluorine plasma dry strip chemistries in limiting silicon loss to 3 Å, even after a total of 16 resist strip steps. (Source: Axcelis Technologies)

The effectiveness of the non-fluorine resist stripping process was demonstrated when a 45 nm advanced logic process line was moved into volume production. When compared with an existing fluorine-containing 65 nm process, the non-fluorine process produced comparable residue defect performance. Moreover, the non-fluorine process was shown to dramatically reduced silicon loss and shifts in R_s, while maintaining the equivalent level of residue defect performance, Han noted.

Selective epitaxy

In some instances, low-temperature selective epitaxy processes are replacing implant/anneal steps, said Gary Miner, CTO for front-end products at Applied Materials (Santa Clara, Calif.). Embedded SiGe (eSiGe) layers, which were introduced to boost PMOS drive current in logic devices, are in situ doped with a high concentration of boron. This allows them to perform the dual role of inducing compressive channel stress for mobility enhancement, as well as serving as the heavily doped drain that has historically been formed by implant and annealing. However, unlike implant, selective epitaxy does not require a subsequent anneal.

Low-temperature selective silicon epitaxy is also being used to form elevated S/Ds that reduce junction leakage and improve memory retention times in DRAM devices. It is already in production at two major DRAM fabs, and will likely be adopted by all DRAM makers at the 5X nm node, Miner said.

Plasma doping

The issue at the forefront for implant is throughput; however, plasma may offer an alternative. For example, the extensions formed on PMOS devices require low boron energies on the order of hundreds of eV, with correspondingly low beam-line current levels, yet a high dose is required (>2 × 10¹⁵/cm^-2). Throughput may be as low as 10 wph. However, that could be increased to >100 wph using plasma-doping methodology, noted Majeed Foad, general manager of doping technology and front-end products at Applied Materials.

Plasma is created within a single-wafer chamber, and a bias is applied to the wafer to attract ions from the plasma. Instead of selecting targeted ion species, everything that is in the plasma is affected by the bias and accelerated to the wafer. In this manner, the total number of ions that penetrate the whole wafer simultaneously as a function of time is at least an order of magnitude higher than the most advanced beam-line tools, Foad said.

The first production applications for plasma doping have been in a poly counter-doping application in DRAM, which requires a high dose (>1 × 10¹⁶ cm^-2) at a fairly low energy. This requirement can be uniquely addressed by plasma-doping technology.

Clearly, the shallow junction area close to the heart of a transistor requires more extensive development, but initial results are encouraging. With an eye on 32 nm and beyond, this is just one among many areas under study in the ongoing development of next-generation junction solutions.