ITRS Lithography Update Weeds Out 45 nm Options

Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 12/21/2007 11:14:00 AM

Although the final chapters will not be released to the public for another few weeks, working group chairs of the International Technology Roadmap for Semiconductors (ITRS) gave presentations at SEMICON Japan earlier this month, highlighting the updates that have been made to the 2007 roadmap.

With leading chipmakers implementing 45 nm half-pitch production today, a significant change to the latest version of the ITRS has been the weeding out of 45 nm potential solutions that simply aren’t ready for that node. “The only things that are available are pretty much 193 nm immersion and double patterning options. And therefore, the other options that were on in prior years just really aren’t ready in time. And it’s really been narrowed down to what you can buy today, and that’s those two,” said Mike Lercel, lithography director at Sematech (Albany, N.Y.) and also U.S. chair of the lithography ITRS working group, in an interview with Semiconductor International.

Listen to the interview (Runtime: 11:11)
Read the transcript

Previously, extreme ultraviolet (EUV) lithography was considered a possibility for 45 nm half-pitch, as well as high-index immersion lithography. “If you go farther back, I think even maskless and imprint were considered options for 45 half-pitch,” Lercel added.

EUV and high-index immersion (as well as maskless and nanoimprint) are still listed as potential solutions for 32 nm half-pitch, but the frontrunner for that node remains double patterning/double exposure. “It’s never an official order, but when we put things in the box for each of these technologies, typically, the one that is the most likely is on top,” Lercel said. “And so if you look at 32 half-pitch, what you’ll also see is the order has changed from the 2006 to the 2007 tables in that the double patterning option – the 193 immersion double patterning – is now the top option, because people are saying, again, that’s what we have that we see can be available for 32 half-pitch development, so that’s probably the most likely. EUV is the second option because many people still consider that certainly the best option because it avoids the double patterning. And then the high-index fluid is the next option.”

Although DRAM has traditionally driven the top-level table numbers for the ITRS, flash memory devices are having an increasing influence on all of the technologies, as well as the roadmap itself. “Just from a timing perspective, the flash companies, the advanced logic companies are really aggressive in terms of starting to introduce 45 nm half-pitch process development today,” Lercel said. “Although we label each of the years by the DRAM half-pitch, and that’s kind of the traditional number, in the tables there’s also a flash half-pitch, which, if you look closely, is accelerated by quite a bit compared to the DRAM half-pitch. And that number drives some of the table entries. But…some of the other entries are driven by either DRAM or MPU, depending on device requirements.”

Another growing influence on the ITRS Lithography chapter is double patterning/double exposure, which the committee members have taken pains to refine in the latest update. “In 2006, it was starting to emerge as an option, so we tried to address it in the roadmap with some fairly generic requirements for double patterning,” Lercel said. “But then if you look very carefully at the different options that are available, there’s multiple ways of doing double patterning, there are different requirements for different types of features. We tried to add some of that complexity to both the text and the table entries in this year. We’re really hoping to provide some guidance for the industry in how do you call out these different entries, and what are some of the different requirements based on device features that we didn’t really address in 2006.”

Although the ITRS committee will come out with complete details sometime in January, highlights of other key lithography concerns include variability, CD uniformity (CDU), line edge and line width roughness (LER/LWR), and overlay. “That gate CDU number is driven entirely by device variability, and that’s a huge challenge in itself, and that’s one where we continue to look ahead and see that that’s a big challenge for the industry to come up with solutions to address that.”

To get up to date with all the major revisions, join Semiconductor International for its webcast, “Highlights of the 2007 ITRS,” Tuesday, Jan. 22, 10 a.m. CST (6 p.m. GMT).