Litho a Major Metrology Challenge

Alexander E. Braun, Senior Editor -- Semiconductor International, 3/19/2008

It is clear from the International Technology Roadmap for Semiconductors (ITRS) that metrology will face some of the most demanding challenges that the technology has ever encountered if it is to continue contributing to the semiconductor industry’s progress toward increasingly complex and application-intensive devices through 2022.

Lithography will be one of metrology’s biggest hurdles, mostly in the area of advanced patterning; three different methods are currently under development to get around straightforward lithographic capabilities. These are double exposure, double patterning and spacer patterning. Because these three methods require different processing, they have different metrology needs.

Alain Diebold, a chair of the International Roadmap Committee’s Metrology Technology Working Group (TWG) and Empire Innovation Professor of Nanoscale Science of the College of Nanoscale Science and Engineering at the University at Albany (New York) puts it this way: “With double exposure, the lithography TWG requires latent image CD metrology, which is something for which, as yet, there’s no known solution. What this calls for, once the double exposure has been done, is the capability to check and see in the resist whether the exposed area has the correct CD before anything further is done. Technologically speaking, this is a tall order.”

Efforts to extend the lifetime of current lithography technology are placing extraordinary demands on technology. (Source: ITRS)

In the case of double patterning, a multilayer process results in the final pattern being smaller than what is possible to print. For double patterning to become viable, there must be a considerable improvement in overlay precision. And, again, metrology is the key.

With spacer patterning, lines are fabricated and an oxide is laid on their sides. Between those oxide sidewalls, which are extremely close together, patterning takes place. This makes the determination of spacer thickness on the sidewall a crucial need and, although there are several possible measurement avenues to approach this, considerable development work may be required.

“These measurements have never been approached at the level of precision that these processes require,” Diebold noted. “There is a number of gaps in metrology technology that will have to be closed before we can address solutions.” With some of the other requirements listed in the ITRS, the good news is that extension of CD-SEM and scatterometry technologies for another couple of generations seems likely.

Stress measurement is one of the new urgent requirement for front-end process metrology. “Considerable time was spent by the other ITRS groups determining what the requirements should be for stress measurement,” Diebold said. “It soon became clear that the requirements for this kind of measurement technique in the lab vs. an inline technique differ. We need to know what is the mobility increase in the transistor’s channel; however, since what one wants to measure is buried, the question becomes whether anything can be learned about what lies below by measuring what is above. This has been an ongoing problem since the 90 nm node, when stress-induced mobility enhancement first hit manufacturing.”

The Emerging Research Materials and Emerging Research Devices TWG discussed all of the different potential transistor replacement switches. With each revision that comes out, more hurdles appear for metrology to defeat. “ERM and ERD covers a great variety of measurement needs. Everything is discussed, from new microscopy to the ability to detect spin and understand what influences it, to the ability to measure electrical properties on these very small devices, as well as measuring the impact of the nanoscale dimensions on their materials properties and subsequently on the device. In addition, the uniformity of these properties must be measured across whatever new kind of chip is manufactured,” Diebold said.

A problem looming over metrologists originates from the fact that the industry is fast approaching the point at which we may begin to influence what we are attempting to measure by the simple act of measuring it. “These are fundamental questions that must be better understood as the new metrology techniques and technologies are developed,” Diebold said. “What’s the probability that you flip the spin while doing the measurement and you end up measuring the wrong thing? All this need to be better understood.”

Metrology often faces a “chicken or egg” challenge in developing new technologies. Researchers tend to plan metrology developments based on their knowledge of known materials and processes. It is becoming apparent, however, especially in the case of litho processes, that while suppliers may plan to perform metrology in a certain way with specific equipment, they may suddenly face a new set of processes that forces them to change their entire approach. Metrologists must become nimble to be able to develop solutions fast enough to meet these kinds of rapid advancements.