Etch's Role in Novel Logic Device Patterning

Double exposure, the consecutive exposure of two masks into the same resist

Self-aligned double patterning (SADP) has emerged as the preferred option for 32 nm NAND flash devices, and is also showing promise for DRAM and logic. Scalability to 22 nm with immersion lithography and SADP has been demonstrated.² SADP avoids the overlay challenges of double exposure because the patterns are created from a single exposure. Mask patterning by SADP involves five etch steps (resist trim, core etch, spacer etch, core or spacer removal, and bottom hard mask etch) that reduce the CD uniformity budget for each individual etch step. Typical 32 nm specifications for the final CD non-uniformity are <1.5 nm 3S. Another etch challenge is caused by the spacer mask. Even small asymmetries in the hard mask shape can cause significant asymmetries in subsequent high-aspect-ratio shallow trench isolation (STI) or gate etching. A good understanding of sidewall passivation mechanisms is critical to overcome this challenge. Thirdly, the need for high etch rates for productivity has spurred the development of novel etch chemistries.

All double patterning techniques require new EDA tools for layout decomposition. New design constraints may have to be enforced to ensure layout compliance with double patterning requirements. Some exciting recent developments have shown that existing 2-D logic structures can be redrawn using "gridded" design rules into 1-D structures that lend themselves to SADP.

Illustration of how a combination of inverter and CMOS transmission gate could be built using the SADP-generated line pattern. (Source: Tela-Innovations and Applied Materials)

3-D transistors were introduced at the 70 nm node in DRAM chips in the form of recessed gates. The gate length for the devices is determined by the depth of the recess trench, hence the device performance is driven by the depth uniformity rather than the CD uniformity. Less than 1% depth uniformity is required in many instances. In the near future, these recessed gate transistors may be replaced by finFET-type transistors. FinFET devices will further tighten the etch depth uniformity requirements and introduce new challenges for selectivity control between silicon and dielectric materials. Because there is no etch stop layer, sophisticated in-process metrology will be required to ensure accurate and repeatable results.

For logic ICs, high-k metal gate transistors are being introduced. The replacement gate integration scheme requires plasma etching of the metal gate and high-k material. High-temperature etching of high-k dielectrics is necessary to provide excellent profile control with no silicon recess and residue-free surfaces.³

In conclusion, the emergence of novel transistor architectures, along with feature size requirements of the 32 nm node, drives the development of new etch technologies. Double patterning, 3-D and high-k metal gates are examples of the latest innovations in the pursuit of the continuation of Moore's Law.