The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation.
3-D, TSV Need Standards and Thermal Solutions to Advance Alexander E. Braun, Senior Editor - 11/19/2008
Yesterday’s sessions at the 3-D Architectures for Semiconductor Integration and Packaging conference indicate that although the technology is progressing and coming into use, there still are unanswered questions about practical, real-world, high-level applications. More
3-D Integration Lacking in Design and Test Support Alexander E. Braun, Senior Editor - 11/18/2008
At a symposium yesterday on 3-D integration, leading expert Philip Garrou detailed the rise of the technology as well as the challenges facing it, including test, yield and design.
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3-D Integration Development Threatened by Economic Uncertainty Alexander E. Braun, Senior Editor - 11/17/2008
As presenters and attendees prepare for the opening of this year’s 3-D Architectures for Semiconductor Integration and Packaging conference, which starts today in Burlingame, Calif., confidence in the technology’s future is mixed with concern about survival in the current economy.
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TMV: An ‘Enabling’ Technology for Next-Gen PoP Requirements Sally Cole Johnson, Contributing Editor - 11/04/2008
After years of R&D, testing and customer evaluations, Amkor’s overmolded/laser ablation technology, a.k.a. through-mold via (TMV), is ready to meet next-generation package-on-package requirements.
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3-D ICs Enter Commercialization Philip Garrou, Microelectronic Consultants of North Carolina, Research Triangle Park, N.C. - 11/01/2008
Among many manufacturers — Micron, Toshiba, STMicroelectronics, Intel, Chartered Semiconductor and TSMC — 3-D integration using through-silicon vias is imminent.
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Kovio Demonstrates RFID Tags Using Printed Electronics David Lammers, News Editor - 10/16/2008
Kovio Inc. (Milpitas, Calif.) announced today at a conference in Chicago that it is demonstrating RFID tags based on its printed ICs (PICs). The startup is getting ready to begin manufacturing at its Milpitas fab, using nine electronics-use inks that it developed internally. “Printed electronics is no longer a vision — it is here,” said CEO Amir Mashkoori.
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Unisem Takes Copper Wire Bonding Process to Volume Production Sally Cole Johnson, Contributing Editor - 10/15/2008
Unisem plans to set up 30% of its wire bonders for copper by 2009. The industry’s interest in copper wire bonding is being driven largely by copper’s enhanced performance characteristics.
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Interposers Play a Key Role in 3-D ICs Kenji Tsuda, Asia Contributing Editor - 10/15/2008
Participants at the Jisso Forum 2008, held recently near Tokyo, emphasized the important role that interposers will continue to play as 3-D interconnects using through silicon vias become more prominent. A Renesas study compared package thicknesses of a conventional flip-chip and an interposer-enabled memory-logic 3-D stack.
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Technical Articles
3-D ICs Enter Commercialization Philip Garrou, Microelectronic Consultants of North Carolina, Research Triangle Park, N.C., 11/01/2008
Among many manufacturers — Micron, Toshiba, STMicroelectronics, Intel, Chartered Semiconductor and TSMC — 3-D integration using through-silicon vias is imminent....
Micro Copper Contacts Replace BGA, Improve Reliability Christopher P. Wade and Sean P. Moran, Tessera Technologies Inc., San Jose, 10/01/2008
In traditional chip-scale and package-on-package configurations, a micro copper contact embedded in the solder interconnection provides improved reliability in drop tests and thermal cycling....
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3-D ICs Enter Commercialization
