32 nm Marked by Litho, Transistor Changes
The transition from 45 to 32 nm is likely to involve some key material changes and a major change in lithography to double patterning for critical layers. Selections will be driven by costs and specific product needs.
Laura Peters, Lead Technical Editor -- Semiconductor International, 1/1/2008
The 65 to 45 nm technology transition is characterized by several changes, including the first adoption of immersion ArF (193 nm) lithography by many companies, the adoption of high-k/metal gates by many logic manufacturers, and continued scaling of low-k in the interlevel dielectric (ILD) of multilevel stacks. At 45 nm, many DRAM and flash makers are also converting from aluminum to copper interconnects. Most importantly, for the first time, flash memory devices (NAND) clearly become the technology driver in terms of smallest feature dimension and pitch. "The shift from 65 to 45 came along with multiple big changes — immersion lithography to get the memory cell density, high-k and metal gate to get more performance from the transistor, and a further step to lower-k in the interconnect," said Hans Stork, CTO of the Silicon Systems Group at Applied Materials (Santa Clara, Calif.) and former senior vice president of the Silicon Technology Development at Texas Instruments (Dallas). "What limits these transitions is time and cost factors. Any of these changes has to be affordable and has to happen in a time frame that makes sense."
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| To achieve specifications, such as 1 nm CD control, process chambers must deliver a consistent process environment regardless of position on the wafer, position in the lot or from one chamber to another. (Source: Lam Research Corp.) |
Because the industry is increasingly driven by consumer electronics, the time frame between product generations continues to shrink while costs must be continually reduced. Despite discussions that the technology nodes might become more spread out, exactly the opposite appears to be happening. "Customers are not relenting on the shrink; they are pushing hard on the path to 32 nm, which is creating demand for double patterning schemes," said Peter Jenkins, head of corporate strategic marketing at ASML (Veldhoven, Netherlands). Stork added, "Reaction times are faster these days, and the cost of invested capital is so high that the chipmaker needs to get the benefit of investments as soon as possible. So the pressure to ramp to entitlement yield is more critical." Stork commented that mature yields above 90% have become the norm in the industry.
The 32 nm litho decisionAt first, it was believed that extreme ultraviolet (EUV) lithography (13 nm) would be delivered in time to satisfy demand for 32 nm half-pitch patterning in the 2009-2010 time frame. Over the past couple of years, it became known that EUV progress was lagging and ArF lithography with immersion would have to be extended using double patterning (DP) as the bridge between 193 nm lithography and EUV. DP involves splitting a dense circuit pattern into two separate, less dense patterns, which are then printed on the wafer. DP is most easily performed on masks with 1-D structures, such as those found on flash memory layouts. Harder are 2-D DRAM and varied logic layouts.1 Depending on the device, there may be 3-5 critical layers requiring DP at the 32 nm node.
Samsung (Seoul, South Korea) recently announced that it would begin producing its 30 nm, 64 Gb flash multicell devices in 2009 using self-aligned DP, also known as spacer-defined DP. Offering advantages in overlay and CD control, spacer-defined dual patterning is just one of the many DP schemes being considered by companies (Table). "Many dual patterning strategies have been proposed, but the optimal choice has not been made yet," stated Luigi Capodieci, AMD fellow and manager of RET/OPC automation and DFM at Advanced Micro Devices (AMD, Sunnyvale, Calif.), during a recent webcast on advanced photomasks hosted by Semiconductor International. Capodieci explained the differences between the approaches: "With the self-aligned scheme, although we can use traditional processes and materials, it is at the cost of multiple masks to define the spacers and more complicated layout decomposition algorithms."
Double exposure, also called contrast enhancement lithography, requires the development of a "memory-free" photoresist, which is not available currently. Double imaging also requires new materials development — the ability to "freeze" the resist pattern, thereby eliminating the first etch step from a typical DP scheme. "In this scheme, a negative resist would actually be more suitable than a positive resist, and research is ongoing, but we don't have a suitable material for production yet," Capodieci said. Finally, there is the traditional DP scheme, which suffers from a large number of process steps (two masks, two exposures, two etches), overlay issues and high costs. The cost difference between spacer-defined patterning, DP and EUV lithography was recently quantified on a cost/layer basis by Jin Seog Choi, CTO of Hynix Semiconductor (Icheon, South Korea), at SEMI's International Trade Partners Conference (ITPC), held in September (Fig. 1).
Figure 2 shows a perfectly aligned layout while the right side shows a shift where some CDs are locally larger than others. This can cause electrical performance degradation in terms of gate width variation, gate length variation, resistance variation, etc. "This error is very systematic, but not very well understood. So studies need to be performed to understand the contribution of a single mask overlay error on electrical performance," he said. With DP, the overlay budget goes from 33% of the CD to 10%. Kurt Ronse, director of lithography at IMEC (Leuven, Belgium), has indicated that overlay is an engineering issue that will be resolved for DP.2
Both Applied Materials and Lam Research Corp. (Fremont, Calif.) offer processes for self-aligned DP. Capodieci noted that one of the most important enablers for DP will be 2-D design rule checking ability. "Most of the critical or 'hot spot' topological situations are caused by discontinuity in 1-D vs. another dimension. So the capability of identifying particular 2-D shapes has become fundamental in design for manufacturability verification," he said. At 32 and 22 nm generations, he noted that restricted design rules and design regularity will be fundamental enablers for manufacturability and yield.
As was the case with dry lithography, more extensive optical proximity correction (OPC) and other reticle enhancement techniques (RETs) will have to be applied to further extend immersion lithography. "By and large, we use phase-shift masks today, but they are the attenuated variety as opposed to the hard shifters, like the alternating PSMs," said Suresh Venkatesan, director of Freescale Semiconductor's Austin Silicon Technology Solutions (Austin, Texas).
Following 193 nm immersion lithography with water medium (NA=1.35), the next logical step seems to be 193 nm immersion lithography using high-index fluids with higher-index lens materials. Fluids with refractive indices in the 1.64–1.65 range are available, but progress with the leading lens material — lutetium aluminum garnet (LuAG) — to date, has not delivered the expected results, including a need to improve absorption by 10-20×.2 "If successful, we expect a high-index system to be available in the 2010–2011 time frame, and this is too late for the first sub-40 nm lithography customers," Jenkins said. "It's almost as if high-index litho, if it does happen, will be a dual patterning technology because it will not intersect customer roadmaps for single patterning applications." However, he noted that research into high-index fluids and lenses continues, and a breakthrough could make a difference in next-generation lithography (NGL).
In the meantime, with the assumption that high-index approaches will not be available, the industry is pushing hard on EUV to be available for production at or before 22 nm half-pitch or around 2011. "22 nm is the main opportunity today, and EUV can possibly backfill into 32 nm if it proves to be more cost-effective," Jenkins said.
The key challenge with EUV from a performance standpoint is simultaneously achieving feature resolution, line edge roughness (LER) and exposure sensitivity. Part of that equation depends on ramping up source power to adequate levels. While gas discharge-produced plasma (GDPP) sources have been used to date, recent laser-produced plasmas (LPPs) now appear to offer great promise. Much progress is still needed. According to Ronse, it remains unclear, for instance, which source approach will ultimately be able to combine high levels of EUV photons with the debris mitigation scheme necessary to protect the collector optics. In addition, photoresists have to be modified. In terms of EUV overlay results to date, Jenkins stated, "We have been able to demonstrate <5 nm overlay, with a CD uniformity of 2.5 nm on 32 nm half-pitch features across a full wafer. These are not production numbers, but this demonstration gives you an idea of the capability."
Transistor changesFigure 3 reflects how the rapid rate of change in structures and materials will continue as chipmakers push the performance of flash, DRAM and logic devices.
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| 3. To continue delivering the performance and power consumption needs of today’s CMOS devices, device manufacturers must adopt avariety of new materials and structures. (Source: IMEC) |
In flash memory devices, new materials and structures may be needed at the 32 nm node. Ken MacWilliams, vice president of Applied Materials' Maydan Center (Sunnyvale, Calif.), stated that it has been development in high-k material and cell design that has allowed the floating gate approach to continue to be extended, pushing out alternatives such as charge trap flash and phase-change memories. "In a stacked device, the high-k enables better coupling from the control gate to the floating gate, while a low-k material between the stacks minimizes possible cell-to-cell interference and acts as filler between the stacks," he said. Here, aluminum oxide or other hafnium-based material is used as the high-k and tantalum or another material can act as the gate.
In the logic world, both IBM (Yorktown Heights, N.Y.) and Intel (Sunnyvale, Calif.) announced their intention to use high-k dielectrics and metal gates at the 45 nm node last year. For these stacks, two integration approaches have emerged: gate-first, where, in a similar manner to existing poly/SiON gates, the gate is subjected to thermal cycles including the high-temperature junction anneals; and gate-last, where a dummy poly gate undergoes heat cycles and subsequent processes, then the dummy gate is removed and replaced with a high-k/metal gate stack (replacement gate approach). The two approaches call for different unit processes.3 At 45 nm, Intel is opting for the gate-last approach, which it will implement using damascene gate processing.
The advantage to gate-last, as described by Reza Arghavani, Applied Materials Fellow, is that all the processing through salicidation does not involve high-k or metal gate. However, because the traditional subtractive approach has been replaced with a damascene integration scheme, the integration is inherently more complex. "The challenge now is you have a poly CD of 35 nm that you have to remove without damaging the high-k dielectric underneath. Then you have to deposit the proper metal on the n-side and the p-side and polish it flat to the top of the gate stack," he described.
Freescale Semiconductor (Austin, Texas), IBM and its other alliance partners are going with a gate-first integration scheme. With this approach, the high-k dielectric and metal gates are deposited using a standard process flow. There is a desire to find a simplified scheme (ideally, one main dielectric deposition and one main metal deposition for both transistors) to minimize costs. The goal is to achieve fairly symmetrical threshold voltages and band-edge effective workfunctions (~4.2 eV for NMOS, ~5.2 eV for PMOS).
From the materials standpoint, hafnium silicon oxynitride (HfSiON) was, at first, envisioned as the easier to integrate between HfSiON and hafnium oxide (HfO2) because of HfO2's susceptibility to crystallization at ~500°C. However, HfSiON provides a limited jump in k value (~15 relative to ~9 for SiON) compared with HfO2 (k~25). "HfSiON tends to put a fairly thick interface between the high-k and the silicon, which helps ease some of the material compatibility issues, specifically when it comes to heat cycles and not-so-desirable electrical characteristics like fixed charge traps and so forth. The drawback is that it's not scalable; so it only provides a single-generation solution for a low-power technology and it is unlikely to be a solution for high performance," Venkatesan explained. Freescale Semiconductor finally settled on a HfZrOx, which, when optimized, provided better interface properties and a slightly higher k value than HfO2. This is used with tantalum carbide-based metal electrodes.
While most early efforts of metal gate evaluation centered on identifying the metal with the appropriate workfunction to control the transistor threshold voltage (Vt), some more recent efforts have concentrated on altering the electric properties of the dielectric, particularly to gain control of the Vt of the pFET device. Aluminum oxide, deposited by RF sputtering onto the HfO2 dielectric, can be subsequently annealed to shift the device's Vt independent of the metal workfunction, resulting in a high effective workfunction and low Vt. A thin TiN/poly gate is then deposited and patterned. For the nFET, Vt control and workfunction modulation is achieved by depositing a lanthanum oxide layer, also by RF sputtering, on the gate dielectric and annealing to form HfLaSiON. Although the exact control mechanism is still being investigated, researchers have indicated that the increase in workfunction and Vt control can be attributed to dipole formation at the interface between the high-k layer and underlying SiON.4 An alternative to using lanthanum to control the nFET threshold voltages involves magnesium oxide. On a 20 nm node device, MIRAI-Selete (Yokohama, Japan) researchers have built W/TiN/HfMgO (nFET) and W/TiN/HfAlO (pFET) gate stacks.5
Gate etches are typically multilayer processes that involve etching through the mask, gate and, in some cases, the gate dielectric. For higher productivity and lower cost, in situ etching through multiple layers in a stack is increasingly required. According to Rick Gottscho, group vice president and general manager of Lam Research's etch businesses, advances in chamber design and advanced equipment control are key to delivering these processes. "In situ etching, where the last layer etched is not the same material as the first layer in the next stack, requires precise chamber pre-coat techniques, so that every wafer sees the same environment," he said. Gate-first approaches call for the ability to control multiple etch parameters (plasma uniformity, wafer temperature and bias voltage) to control CD and etch profile. He added that high-k/metal gates require methods to minimize CD change while improving selectivity to the underlying film. "In cleaning, a key way to minimize CD change is to minimize the wafer exposure time to cleaning chemicals."
Another high-k/metal gate alternative uses fully silicided (FUSI) polysilicon gates. Here, the nickel is deposited on poly and completely silicided, forming different phases of silicide for the nFET and pFET, respectively. Challenges in a FUSI flow include achieving full silicidation across various features and maintaining phase, the latter of which can be aided by hard masks. With FUSI, workfunction tuning can be achieved by implanting ytterbium into the poly of the nFET and gallium into the pFET. The placement of the tuning elements at the metal/dielectric interface must be engineered with the thermal budget, as well as the implant dose and species.
Strained siliconLast year at this time, we showed how various stressor techniques will be used at the 45 and 32 nm nodes to improve the mobility of charge carriers in the channel (electrons in nFETs and holes in pFETs).6 The most cost-effective techniques include nitride caps over the nFET that induce tensile strain in the channel and nitride caps over the pFET that induce compressive strain in the channel. Arghavani stated that compressive stress levels of 4 GPa are now achieved in production and, with UV curing, tensile stress levels of 2 GPa are possible. The extendibility of this technique appears to be mostly limited by real estate concerns — having enough room around the transistor to wrap the nitride layers.
Gottscho said that the introduction of strained silcon has increased the number of multilayer etches and requires the ability to stop on silicides with minimal film loss. "Recently, we are seeing interest in so-called disposable spacers that allow placement of stressed nitride closer to the channel after implantation," he said.
Another widely used, although more costly, stressor technique uses epitaxially grown silicon germanium (SiGe) in the source/drain (S/D) regions of the pFET. A similar approach can be used to grow SiC in the S/D regions of the nFET.
A technique called stress memorization uses poly implants and a stress transfer film that is annealed and removed, leaving a memorized tensile strain in the nFET. Strained silicon on insulator (SOI) substrates are available although, to date, they have not been adopted in manufacturing. "This is the only technique available with strain inherently built into the substrate. So we continue to pursue it, but it takes a while to take advantage of something new," Venkatesan said.
An even "newer" approach involves creating high-mobility channels, the first of which is likely to be germanium. But it is important to note that part of the success of the high-k/metal gate implementation has relied on maintenance of the Si/SiON interface from previous generations of devices. "If one thing is at the heart of the performance of the transistor, it's that interface between the channel and dielectric, so changing it would be a monumental transition," Stork said. High-mobility channels are not expected to be implemented before 22 nm, if then.
FinFETsMultigate devices like finFETs have superior electrostatic integrity and control over short-channel effects. Essentially, by containing or fully surrounding the channel with the gate, the electric field is nearly uniform throughout the channel. As a result, the transistor behaves like a fully depleted device. Some of the advantages to the design are the complete lack of well implants, no latch-up, and reduced parasitic capacitance and resistance problems associated with shrinking space between transistors.
Perhaps the biggest obstacle to finFET adoption is a lack of industry consensus that it is the right transistor structure for all devices. In addition, making the transition from 2-D planar devices to 3-D structures is complex and difficult from a design and manufacturing standpoint. "Anyone in the industry would say they will start using it only when they absolutely have no other choice, right? Because it is a 3-D device, it is inherently more complex to manufacture with the same precision," Stork said. However, for certain device types such as SRAM, the reduced short-channel leakage current makes the finFET structure very attractive.
| References |
| 1. A. Hand, "Double Patterning Wrings More From Immersion Lithography," Semiconductor International, February 2007, Vol. 30, No. 2, p. 40. |
| 2. L. Peters, "Double Patterning Leads Race for 32 nm," Semiconductor International, Oct. 18, 2007. |
| 3. R. Arghavani, G. Miner and M. Agustin, "High-k/Metal Gates Prepare for High-Volume Manufacturing," Semiconductor International, November 2007, Vol. 30, No. 12, p. 32. |
| 4. R. DeJule, "A Step Up for High-k CMOS," Semiconductor International, October 2007, Vol. 30, No. 11, p. 17. |
| 5. P. Singer, "IEDM Focus: Metal Gates/High-k for 45 nm," Semiconductor International, October 2007, Vol. 30, No. 11, p. 24. |
| 6. L. Peters, "45 to 32 nm: Another Evolutionary Transition," Semiconductor International, January 2007, Vol. 30, No. 1, p. 42. |
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