High-k/Metal Gates Prepare for High-Volume Manufacturing

Smaller transistors require an increased capacitance gate dielectric to control short channel effects. This is achieved by reducing gate oxide thickness, but this increases gate leakage. Below a 5.0 nm thickness, leakage is unacceptably high when SiO₂ is used as a gate dielectric material. Thus, IDMs introduced nitrided oxide (SiON) as a gate dielectric. This change offered three main advantages. First, in PMOS devices, boron penetration from poly into the gate dielectric is significantly reduced, leading to reduced threshold voltage (V_t) variation. Second, hot electron performance is improved for NMOS devices. Finally, these benefits offer the added advantage of an enhanced dielectric constant and lower electrical thickness.

An ALD process chamber is used to deposit films with atomically engineered interfaces. (Source: Applied Materials)

The solution was to replace the oxynitride with a higher dielectric constant material that allows a thicker dielectric to be deposited to reduce leakage without electrical thickness penalties. This is because the equivalent oxide thickness (EOT) of a dielectric is inversely proportional to its dielectric constant:

T_high-k is the high-k dielectric’s physical thickness and ε_high-k is its permittivity. For a given dielectric thickness, a higher dielectric constant leads to lower EOT. Replacing oxynitride with a higher-k material allows a higher capacitance without electrical thickness penalty and improves gate leakage. For a given gate dielectric thickness, the hafnium-based (Hf) high-k dielectric coupled with a metal gate reduces gate leakage by several orders of magnitude, allowing scaling of the transistor’s poly CDs.

During early high-k dielectric development, material incompatibility between it and the poly gate electrode was discovered.^3-5 At issue were high defect rates at the interface of high-k and polysilicon and the device’s lower electrical mobility. The latter was attributed to charge scattering, which is intrinsic to the physics of an integrated poly and high-k device.⁶ The early solution was replacing polysilicon with a metal electrode. High-mobility devices with high-k gate dielectric and TiN electrode (a mid-gap metal work function) were processed and successfully circumvented mobility issues.^6,7

Because CMOS processing requires both NMOS and PMOS devices, high-k/metal gate implementation now requires three new materials: one high-k dielectric; a metal (replacing poly) that works for NMOS (4.2 eV); and a metal that works for PMOS (5.2 eV). This constitutes the classic material requirements of two “work function” metals (properties capable of achieving V_t) and one dielectric method.

An alternative implementation of high-k/metal gates eliminates the need for two different metals by depositing two different dielectrics: a hafnium-based dielectric with another dielectric containing more electropositive atoms, such as lanthanum oxide in the case of NMOS devices. The built-in dipole field in the dielectric adjusts the device’s V_t independently of the metal work function. For PMOS devices, the hafnium-based dielectric must be paired with a dielectric containing more electronegative atoms, such as an aluminum-based oxide. These approaches require different materials, integration methods and even tool sets in high-volume manufacturing.

New high-k gate dielectrics

Hafnium-based dielectrics are the material of choice to replace SiO₂.^4-8 Hafnium-based dielectrics include hafnium oxide (HfO₂, k≈25) for high-performance ICs such as microprocessors; and hafnium silicate/hafnium silicon oxynitride (HfSiO/HfSiON, k≈15) for low-power-consumption chips. HfO₂ provides a higher k, but can be harder to integrate because it crystallizes at lower temperatures (~500°C) unless thin enough and properly capped. The addition of silicon to form HfSiO improves thermal stability at the expense of lower k. Nitridation forms HfSiON, improving thermal stability and enabling the film to remain amorphous up to source/drain (S/D) anneal temperatures of ~1050°C, slightly increasing the k value while decreasing gate leakage.

1. No hump in CV curves measured from an integrated SiON and HfO2 stack with metal gate indicates an atomically smooth interface. Inset shows the high-k/metal gate with a thin SiON interface and the SiON/HfO2 transition layer that increases the net k value and enables electrical thickness scaling.

The expected increase in electrical thickness caused by a lower-k oxynitride addition in series with the high-k material is offset by the mobility gain that drives device performance. Figure 1 shows capacitance-voltage (CV) curves measured at low to high frequencies. The plotted CVs are the same and show no humps that indicate interface traps. This result confirms that the oxynitride layer provides a high-quality interface between the high-k and silicon channel. Some intermingling of hafnium with the oxynitride interface occurs during processing and increases the net k value of the stack (i.e., electrical thickness is reduced).^9,10 High-mobility devices can be expected from the integrated oxynitride and high-k stack with scaled electrical thickness.

New metal gates

Replacing polysilicon gate materials with metal eliminates compatibility issues between the high-k dielectric and poly electrode. Hafnium-based high-k dielectrics were successfully integrated with TiN metal gates, producing transistors with a high mobility channel. Significant effort and research was focused on finding metal electrodes with the correct work function.^6,7 However, work function metals of 4.2 and 5.2 eV are needed to adjust the NMOS and PMOS devices’ V_t. Such metals must withstand current CMOS integration thermal requirements where high-temperature dopant activation is used. Most metals with high work function have stable bulk characteristics after high thermal processing. However, these metals alter their interface characteristics with the high-k dielectric after high-temperature processing. This thermal instability can manifest itself as V_t variation and decreased device reliability. Furthermore, a V_t shift >0.5 eV on PMOS devices processed with high-k and positive work function metal gate can occur after high-temperature processing. The cause is oxygen vacancies in HfO₂ caused by metal deposition processing and subsequent high-temperature processing.⁶ Simultaneously, metals with mid-gap and low work function are less stable with respect to high-temperature processing because their bulk characteristics change.

Because conventional CMOS processing is incompatible with metal gate electrodes, a new low thermal budget CMOS flow was needed. Such a process could be a gate-last or damascene flow.^6,11-14 In this flow, metal gate materials are deposited inside poly trenches after thermal processing and dopant activation. Trenches can be created after salicidation and stress-inducing layer processing. In a gate-first flow, however, V_t must be adjusted by alternative methods, such as the creation of a dipole field inside the dielectric that adjusts V_t independent of the metal’s work function.^15,16

The tool set required for metal deposition is a combination of physical vapor deposition (PVD) and atomic layer deposition (ALD). Depending on the integration method, ALD, with its ultrahigh step coverage, could be used first to fill the narrow-CD poly trenches, followed by advanced PVD technology. Where the dielectric itself must be modified to adjust V_t, PVD sputtering of the V_t-tuning dielectric could be used; a single metal deposition independent of its work function is required.

Significant advances have been made in ALD, PVD metal and dielectric deposition, as required for device V_t tuning (i.e., metallization and dipole-inducing dielectrics). Tool sets for implementing high-k/metal gates are ready for high-volume manufacturing.

Etch, CMP and metrology

High-k/metal gate implementation introduces new etch, chemical mechanical planarization (CMP) and metrology challenges. In the gate-first scheme, both the dielectric cap layer and metal gate deposition must be low-damage processes with excellent uniformity. High-k materials present profile, selectivity and residue control problems that require a wider process window to overcome. To ensure the device’s ultimate electrical viability, high-k etch must achieve vertical and smooth profiles down to the silicon interface and avoid any recess into the silicon in the S/D areas beneath the gate.

Avoiding silicon recess calls for a chemical etch that eliminates the risk inherent in physical bombardment by reactive ion etch (RIE). However, at conventional processing temperatures, etching cannot clear a full vertical profile down to the silicon interface. Instead, it tends to leave behind a foot-shaped film of the high-k material at the interface and generates undesirable residue. High-temperature etch processing, however, energizes the chemical etch action to eliminate the foot with infinite selectivity to the underlying silicon while enhancing high-k etch byproducts’ volatility to produce residue-free surfaces (Fig. 2).

2. Higher substrate temperature increases the chemical etch component, which removes the high-k foot while maintaining a vertical profile.

For the gate-last flow, new polishing techniques must be developed to remove the low-resistivity metals used to fill poly trenches. Such a process must maintain uniformity without electrode dishing, as this could lead to subsequent contact lithography and processing issues.

Detection of small defects between dense structures requires a coherent, high-intensity illumination source, such as a short-wavelength laser, to penetrate between the structures without losing inspection sensitivity. The anticipated variety of new defect types also requires detection mechanisms to collect defect signals from multiple angles and the right algorithms to filter out material and pattern noises, leaving only signals from defects of interest. With the introduction of new materials in high-k/metal gate processes, defect composition analysis and cross-sectioning of defects are essential methodologies to shorten the yield learning curve during the development phase and find the root causes of excursions during production.

Several integration schemes are being considered, with the two main approaches being “gate-last” and “gate-first.”

Gate-last

The gate-last approach (Fig. 3) is considered a low-temperature process because metal gate deposition occurs after the activation anneals, and the metal is not exposed to high temperatures. In the gate-last integration flow, the high-k film is deposited prior to poly deposition. Thus, it goes through the standard process flow up to salicidation and stress-inducing nitride layers processing (dual stress liners). An oxide gap-fill layer is then deposited between the poly lines and polished to the poly. The poly trench etch is done simultaneously for both NMOS and PMOS, followed by metal gate deposition and metal fill. In such structures, the metal gate deposition requires complete step coverage without high-k damage. One lithography step is required to remove the first metal deposited, which depends on whether the NMOS or PMOS metal gate is more easily etched. With the advantage of knowing what metal gates to use for this low-temperature integration, the challenge is filling the structures. One metal fill step is needed to fill the trenches without voids or seams. A final metal CMP step removes the excess metal. This will require consistent monitoring and an appropriate final clean that does not affect the device. A standard process flow would follow, beginning with a second pre-metal dielectric (PMD) layer and contact etch.

3. Gate-last integration is a low-temperature metal gate process. The high-k is deposited prior to poly and undergoes a standard process flow. After PMD deposition and CMP, the poly from both NMOS and PMOS are removed simultaneously. After metal gate deposition, one lithography step is required to remove the first metal deposited. Finally, complete metal fill and a metal CMP are required.

Gate-first

In the gate-first integration flow (Fig. 4), with the exception of inserting the high-k/metal gate, a standard transistor process is used. To avoid the influence of high thermal budget on the metal’s work function, a mid-gap, thermally stable thin metal layer is deposited on both NMOS and PMOS devices. V_t is adjusted by dipole engineering of the dielectric independent of the mid-gap metal electrode. This is done by creating a dipole field inside the dielectric. A hafnium-based dielectric is deposited, followed by a dielectric cap layer that intermixes with the HfO₂ upon high-temperature annealing and creates a dipole, shifting the V_t.

4. Gate-first integrates the high-k/metal gate steps into the standard process flow. The dielectric cap layers are deposited after the blanket high-k deposition on the oxynitride. One lithography step is required to remove the first cap layer. A single metal is deposited on both cap layers, which tune the device threshold voltage (Vt).

In general, for a hafnium-based high-k dielectric, a more electropositive element shifts V_t toward NMOS, and a more electronegative element shifts the work function toward PMOS. Lithography steps follow to remove the initial dielectric cap layer from the PMOS side. The PMOS dielectric cap layer is then deposited and removed from the NMOS side. Because V_t is tuned by the respective dielectric cap layers, a single metal is then deposited for both NMOS and PMOS, followed by poly deposition (Fig. 5).

5. Two main integration schemes are being considered for high-k/metal gate implementation: gate-last and gate-first.

High-k/metal gate in CMOS memory

Flash memory technology is driven by aggressive lithographic scaling to increase bit density. This scaling brings about device and material limits with the current floating gate (FG)-based flash memory unit cell. In NAND memories, the FG unit cell is programmed by Fowler-Nordheim (FN) tunneling of electrons through the bottom oxide and into the polysilicon floating gate. The electrons are trapped in the FG by the adjacent oxide layers’ large conduction band barrier. This alters the cell V_t. The cell is also erased by FN tunneling through the bottom oxide. With scaling, FG cells are brought into closer proximity, and because trapped electrons are mobile within the FG, adjacent cells can interact with one another to alter their V_t. Additionally, to create sufficient coupling between the control gate (CG) and FG, the interpoly dielectric is wrapped around the sides of the FG in the word line direction. The wraparound technique is unfeasible for aggressively scaled arrays and, therefore, sufficient CG-FG coupling becomes problematic with future scaling of FG memory.

Thus, novel materials and device configurations have been investigated, such as 3-D SONOS arrays,¹⁷ resistive RAM (including chalcogenides), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), nanocrystalline and high-k/metal gate charge-trap flash. Among these, leading memory IDMs have explored the use of high-k/metal gate with charge-trap flash devices, such as the TANOS (TaN-Al₂O₃-SiN-oxide-silicon) cell structure.¹⁸ FN tunneling is also used for programming the charge-trap nitride cell; however, electrons are stored in discrete traps in the nitride storage layer’s energy bandgap. Because the stored charge is less mobile and localized, interaction with adjacent cells is minimized, promising lateral scalability below the 40 nm node.

With the addition of a higher-k material for the charge-trap device’s top-blocking dielectric, a larger electric field is transferred to the tunnel oxide. This increase in electric field allows for faster program/erase speed, reduced operating voltage, and the implementation of a thicker tunnel oxide to improve retention without compromising device speed. The top high-k dielectric must also have a wide bandgap (e.g., Al₂O₃) to block electron flow to the gate during program and inhibit electron leakage in retention mode. During the erase operation, holes tunnel from the substrate to the nitride layer and drive V_t of the cell to a lower value. Simultaneously, electrons may back-tunnel from the gate into the charge-trap layer. When the electron current becomes equivalent to the hole erase current, the negative V_t shift ceases. This is alleviated by coupling a high work function metal gate with the high-k dielectric to increase the electron barrier height, reducing the back-tunneling current.¹⁸

Challenges with high-k metal gate implementation in the flash memory process flow are similar to the logic gate-first process in terms of material stability and variability with high-temperature processing. However, only a single metal with a high work function and high-k dielectric is used for all cells.

At the 45 nm node, logic devices will implement high-k and metal gates into the process. Flash memory can take advantage of high metal work functions and bandgap-engineered charge-trap memories by implementing high-k and metal gates. Two metals and one dielectric vs. two dielectrics and one metal are approaches taken by leading logic device manufacturers. Each choice, however, requires a unique integration scheme and tool set. Both the equipment industry and leading device manufactures are ready to put this change into high-volume manufacturing.