AMD Building Advanced Development Center in Push for Shorter Cycle Times

David Lammers, News Editor, and Peter Singer, Editor-in-Chief -- Semiconductor International, 10/24/2007 8:53:00 AM

As part of its emphasis on small-batch processing and lean manufacturing, Advanced Micro Devices Inc.  (AMD, Sunnyvale, Calif.) is building an advanced development center in Austin that is expected to be in operation early next year.

During a keynote speech Wednesday (Oct. 24) at the International Sematech Manufacturing Initiative (ISMI) Symposium going on in Austin, Doug Grose, senior vice president in charge of manufacturing and supply chain at AMD, made brief reference to the development center, saying it was part of AMD’s emphasis on reduced cycle times, improved tool predictability and “mini batch tools.”

“The blind focus on raw capacity” is butting up against the need to make a wide variety of products, with much faster cycle times, Grose said. “We need to reduce waste and reduce the cycle time, and to do that, the industry needs to discover the issues that factor into our cycle times. Cycle time reduction is not new, but it makes more sense and is more important than ever.

“We have to understand where we lose time. When we process 25 wafers, those wafers spend a lot of time waiting. Smaller lots help, smaller batch tools help. It is all part of a lean transformation that builds on advanced process control software, which gives us accuracy and agility,” Grose said.

Asked to clarify the role of the advanced development center, AMD spokesman Gary Silcott said it was too early to discuss the center in detail. AMD is currently installing tools, overhead track and other equipment at an abandoned warehouse on Austin’s south side, a Congress Avenue building that has the 14 ft ceilings required to accommodate overhead track height, he said.

The goal is to recruit tool vendors and other suppliers to provide the equipment needed to test out smaller batch lots, combining the hardware with AMD’s APM software and other tools. “It is being driven by AMD, but a lot of the tools are being contributed. We are interested in getting other companies to join with us,” Silcott said.

Gerold Goff, a senior member of the technical staff at AMD, is working with suppliers now to create the center. Goff recently organized a Sept. 12 meeting in Austin of 21 companies, including six chipmakers and equipment suppliers, to discuss an AMD-led Next-Generation Factory initiative. AMD, Freescale Semiconductor, IBM, Qimonda, Renesas Technologies and Spansion sent representatives to that meeting.

In his ISMI keynote, Grose put the smaller batches into the larger context of lean manufacturing, and juxtaposed the efficiencies possible with lean manufacturing with the traditional emphasis on moving to larger wafer sizes and rapid shifts to new process technology nodes. As a result of those large-sized shifts, 300 mm fabs cost 250% more than 200 mm fabs, and the cost of going to a new process node is four times higher now that in the recent past.

Rather than make such large and expensive jumps in wafer size and complexity, Grose said the industry should make smaller, continuous improvements. Partly because of the complexity of its products, Grose said the industry “is a prisoner to inertia, too cautious to break with the past. We have a manufacturing and supply chain that is Byzantine in complexity,” he said, one that is “locked in unproductive concepts.”

The emphasis on smaller batch sizes reflects AMD’s changing product mix. Grose said that when AMD acquired ATI Inc. last year, it found itself challenged to incorporate ATI’s broad product portfolio of graphics chips, consumer ICs and PC chipsets.

Also, AMD’s own MPU products are becoming more numerous, a trend that is likely to continue as the company moves to a core-based “Fusion” product lineup in 2009 that will combine CPUs, graphics cores and other elements, some based on the X-86 architecture, some on other cores. And AMD is investigating which of those products should be fabbed in its silicon on insulator (SOI) high-performance process and which can be made on bulk silicon wafers.

Experts cite a long list of advantages to reduced cycle times, including:

• faster response to changes in customer demand (up or down)
• overall cumulative yield tends to increase as cycle time is shortened
• high exposure to manufacturing process issues (faulty die may be discovered faster than the conventional 90+ days at assembly and test)
• faster learning curves
• smaller monetary investment in wafers in process (150,000 wafers × $2500/wafer=$375M)
• improved responsiveness to new customer opportunities
• improved investment for storing/managing WIP (stockers for 5000-10,000 FOUPs)
• improved exposure of wafers to lengthy and unpredictable dwell times between process steps (wafer surface state variability)
• shorter duration feedback loop between metrology and processing impairs process control