Unexpected nFET Gains for 110 Silicon
David Lammers, News Editor -- Semiconductor International, 1/14/2008 9:27:00 AM
The future of CMOS may switch from the 100-oriented crystalline silicon used throughout the semiconductor industry today to 110-oriented wafers, according to Sematech (Austin, Texas) researcher Rusty Harris.
 |
| Rusty Harris, Sematech research manager |
The bottom line: a significant 15% improvement in ring oscillator performance for the 110 silicon, at no apparent increase in cost or process complexity.
 |
| A ring oscillator showed a 15% speedup in 110 silicon. |
The research builds on the development of high-k/metal gate technology over the past few years, solving the nFET mobility degradation and the pFET threshold voltage stability issues.
“Once we fixed the interface states which caused scattering, we found that the transistors scale so that velocity saturation dominates,” Harris said in an interview at Sematech following presentation of the research at the International Electron Devices Meeting (IEDM) in Washington, D.C., last month. Thompson had predicted that at smaller device dimensions, velocity saturation, in which drive current no longer increases once a certain level of voltage is achieved, would be the dominant real-world factor limiting nFET performance, rather than simple electron mobility or linear drive current.
An initial study was performed in 2006 by S. Krishnan, then a University of Texas graduate student working as a Sematech intern, who is now an IBM researcher. Krishnan published that work at the 2006 IEDM.
In 2007, Harris led an effort that fabricated devices with channel lengths of 80 nm, made in a 130 nm process technology. Harris said the result was “symmetric performance for nMOS and pMOS. The curves are nearly identical. That means that we get all the benefits of 110 pMOS, without the degradation predicted earlier for nMOS.”
 |
| In 110 silicon, pMOS devices are roughly symmetrical to the nMOS transistors. |
Raj Jammy, the front end program manager at Sematech, said electron mobility is degraded in the 110 silicon, compared with 100. However, independent of the lattice orientation, nFET performance depends not on mobility but on velocity saturation. Since there is not a big difference in velocity saturation for either crystalline orientation in the nMOS transistors, the gain in the pMOS transistor performance offers speed benefits at little or no additional complexity, he said.
Jammy said that with higher-performance pFETs, companies would be able to achieve symmetry between the nFETs and pFETs. That would permit smaller pFETs than required today, yielding improvements in transistor density.
Also, the switch to 110 does not appear to impact leakage currents, either gate-induced drain leakage (GIDL) or other causes of leakage. That is important for companies seeking to improve performance while keeping power consumptions, and costs, roughly the same.
Harris said the pFET performance is roughly 1 mA/µm, which he said is nearly as good as the pFET presented at IEDM by Intel Corp. for its 45 nm technology. “Once we’ve done the right junction engineering, we get symmetric performance of about 1 mA/µm. Intel and TSMC are about that for their pFETs. And we are very near that without using strain techniques, and with larger gate lengths and an extremely simple flow,” Harris said, adding that the improvements “should be more exaggerated as we go to shorter gate lengths.”
The interest in 110 silicon has increased in recent years, as IBM and others have studied the possibility of using 110 silicon for the pFETs and 100 silicon for nFETs on the same wafer. That hybrid orientation technology (HOT) approach usually involves using epitaxial deposition, and silicon-on-insulator (SOI) wafers. The end result of one hybrid approach is to create a 110 SOI device for the pFET, and a 100 bulk silicon device for the nFET. However, the process complexity, yield losses and added costs were seen as barriers for most applications.
Harris said Sematech has studied the use of 110 silicon for finFETs and found that the performance gain holds for the vertical devices, which are fabricated on SOI wafers using fully depleted CMOS.
Also, because the openings in the lattice are larger with 110 silicon, the switch to 110 affects the depth of ion implantation in the junctions to the source and drain regions. To keep the desired shallow profiles, the Sematech team used well-known germanium roughening techniques to create amorphous silicon in the source and drain regions. That improved the dopant profiles.
“We did further studies to understand the impact on the junctions,” Harris said. “When we do high-energy implantation, the ions can channel through more easily because the silicon spacing is larger. That caused a slight difference in both junction depth and overlap.”
Asked if the chip industry is likely to eventually make a major switch to 110 wafers, Harris said, “We do see this having an impact.”
Jammy said Sematech will continue to do the fundamental research this year, as it transfers its accrued knowledge out to the Sematech member companies. “The next step is to try and incorporate it in other devices, which are dimensionally scaled, with diifferent gate stacks. There is potential for next-generation memory work and for high-performance as well.”
Talkback
Related Content
Related Content
SPONSORED LINKS
SI Resource Center
Browse Resources by Type:
- Industry Survey of Wafer Fab Reticle Control Quality Strategies
Ieee Operations Center | White Paper
VIEW NOW
Ieee Operations Center | White Paper
VIEW NOW
Ieee Operations Center | White Paper
VIEW NOW
View More
