CMOS on (110) Silicon May Have Cost Appeal
David Lammers, News Editor -- Semiconductor International, 1/23/2008 8:01:00 AM
Cost-sensitive consumer ICs may be well-served by CMOS on (110)-oriented silicon, although the question remains “to-be-decided,” said Scott Thompson, a professor at the University of Florida (Gainesville, Fla.).
 |
| Scott Thompson, professor at the University of Florida, is studying strain enhancements on (110) silicon. |
 |
| Rusty Harris, Sematech |
Thompson and Harris, along with 10 others from Sematech, published a paper at the International Electron Devices Meeting (IEDM) held in December on (110) CMOS. Sematech and the Sematech member companies, among others, are pursuing the research. Over the past year, Thompson said he has received for evaluation several (110) CMOS wafers from IC companies, which he declined to name other than to say they are seeking a low-cost means of boosting logic performance for consumer applications.
CMOS on (110) silicon could be a cheaper way of boosting planar CMOS performance than the route taken by the high-performance chip vendors, which have embedded silicon germanium (eSiGe) at the PMOS source and drain regions to induce compressive strain in the channel. That eSiGe technique, highly effective on PMOS transistors on (100) silicon, depends on expensive epitaxial deposition and tends to be too expensive for low-cost applications, Thompson said.
“I am a real believer that we all need to focus on these low-cost markets. To date, no one has put embedded SiGe into a low-cost market; it is used only in the higher-cost MPU markets,” he said.
Embedded SiGe can create very high levels of PMOS strain: >2 megapascals. A key area of investigation is whether eSiGe works as well with (110) silicon as it does with (100) silicon. An IBM paper at IEDM indicated that eSiGe works well on (110) silicon, but Thompson said his research shows that (110) PMOS devices respond well to relatively moderate levels of strain, <2 megapascals. Using a jig to bend the wafers and create mechanical strain, Thompson, along with a former University of Florida graduate student, Guangyu Sun, and others studied PMOS performance on (110) silicon with different levels of strain. They published their results last year in the Journal of Applied Physics.
While noting that “others have different views,” Thompson said eSiGe improves (110) CMOS to a lesser extent than (100) CMOS. “It depends on what level of stress you are looking at. At high levels of stress, (100) silicon may be better, but for low levels of stress, there still is a 2× gain. Basically, it all depends on each company, on how well that company integrates with other enhancers, like eSiGe. None of them are perfectly additive. At less than 2 gigapascals, there is good additivity with (110) CMOS. It may take a a couple of years to fully answer these questions, and I think we will see this play out over the next couple of years at IEDM and other conferences.”
(110) for low cost, (100) for high performance
If eSiGe on (100) silicon results in higher performance than (110) CMOS, the result could be a bifurcation: high-performance chips made on (100) silicon with eSiGe to wring out the highest planar CMOS performance, while low-cost ICs could be made on (110) silicon without eSiGe.
“Most companies can do eSiGe with one mask layer, but the epitaxial process itself is costly. On these multi-million-dollar deposition tools, we get throughputs in the single digits per hour. That is a bottleneck in terms of throughput — about one-tenth of what you want it to be for low-cost silicon,” Thompson said.
The use of (110) CMOS would continue a trend toward near parity for the NMOS and PMOS transistors. The 80 nm channel length devices fabricated at Sematech showed roughly similar performance for the NMOS and PMOS devices. A 1:1 beta ratio would improve the packing density by reducing the width of the PMOS devices.
 |
| At IEDM, Sematech reported roughly equal drive currents for NMOS and PMOS devices on (110) silicon. |
However, a sudden shift in the beta ratio might trouble some design teams, which would need to adjust their circuit models to account for the stronger PMOS devices, said one source at a major logic manufacturers, who asked not to be identified.
The source said he still questions whether the Sematech (110) CMOS study is valid. The device data from the Sematech paper “was very poor. A 15% performance boost on a poor device [probably a few tens of percentage points lower performance than any competitive transistors] is not that useful,” the source said, adding that he believes that (100) CMOS devices with state-of-the-art junctions and optimized stress engineering will outperform similarly enhanced (110) CMOS.
Harris said that Sematech is working on (110) CMOS devices with various strain enhancements and shorter channel lengths. And he noted that even at 80 nm channel lengths, the PMOS devices in (110) CMOS have roughly the same performance as Intel’s 45 nm generation PMOS transistors, at roughly 1 mA/µm drive current.
Will (110) CMOS take its place in the industry?
Too early to tell, Harris said. “(110) is certainly simpler than other approaches to improving performance, with obvious benefits right out of the box. That makes it important from a cost-benefit perspective. This may be the cheapest method of getting performance enhancement for both high performance and low power. It doesn’t lean one way or the other.”
Talkback
Related Content
Related Content
SPONSORED LINKS
SI Resource Center
Browse Resources by Type:
- Industry Survey of Wafer Fab Reticle Control Quality Strategies
Ieee Operations Center | White Paper
VIEW NOW
Ieee Operations Center | White Paper
VIEW NOW
Ieee Operations Center | White Paper
VIEW NOW
View More
