MIRAI Team Studies Threshold Voltage Variation Causes

Kenji Tsuda, Asia Contributing Editor -- Semiconductor International, 1/7/2008 8:33:00 AM

With transistor threshold voltage (V_t) variability now a top-shelf concern, a group of researchers led by Toshiro Hiramoto at Japan’s Millennium Research for Advanced Information (MIRAI, Tokyo) consortium  have studied the role of dopant levels and other factors.

The MIRAI team determined that V_t variation of nMOS transistors depends only in part on dopant variations, with the flat-band voltage, the thickness of the inversion layer, sheet charges due to surface states, fixed charges in the oxide, and dopant pile-up at the interface also contributing.

The Hiramoto team prototyped a 2 million-transistor array in 65 nm technology, divided into 1 million n-channel and 1 million p-channel transistors. After measuring V_t variation, the team concluded that although pMOS transistors show a V_t variation largely caused by impurity fluctuations, the nMOS transistors are impacted by a wider array of factors.

MIRAI researchers studied the role of dopant fluctuations, and other factors, in threshold voltage variability.

The Hiramoto group prototyped chips with 26 test element groups (TEGs). Each TEG has 20 sub-chips. The arrays were aligned in the same direction. The team evaluated MOS transistor characteristics, including V_t and sub-threshold current.

The results showed a Weibull distribution among a total of 100 million tested transistors. The V_t variation data showed a linear change, in a Gaussian distribution. 

The V_t ranges from +5σ (standard deviations) to -5σ for nMOS and pMOS transistors. A single variation (1σ) of V_t was 43 mV for the p-channel transistors and 65 mV for the n-channel transistors.

To find out the causes of the variations, the team said it concluded that the V_t variation is expressed with a root of (T_ox + 0.8 nm)(V_t + 0.1 V) / LW, rather than with the conventional root of LW, where L is gate length, and W is gate width. (T_ox + 0.8 nm) shows an effective gate oxide thickness at a MOS inversion state, and (V_t + 0.1 V) shows an addition of the flat-band voltage of the work function difference between the gate metal and a semiconductor with a surface potential contribution of 0.1 V, shown in an equation of qNW_dep/C_ox, where W_dep is depletion width and C_ox gate oxide thickness.

In their experiments, the results differed for pMOS and nMOS transistors. For pMOS transistors, a gradient of the V_t variation is independent of impurity concentrations. The gradient is always constant. For nMOS transistors, however, the gradient is not constant, increasing with dopant concentrations and smaller gate lengths. The team now is developing methods to measure the oxide thickness variations and surface roughness, and is creating simulation models to support its work.