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On Mobility, Velocity Saturation, and (110) Silicon
January 28, 2008
In recent years, the chip industry has pulled a couple of rabbits out of the proverbial magician’s hat: uniaxial strained silicon and immersion lithography. Will (110) CMOS be the next rabbit?
First, please step back a decade. IBM researchers, including Min Yang and many others, grabbed on to the concept that holes move faster in (110) oriented silicon lattices. They argued that a hybrid orientation technology (HOT) would be worth the extra effort, and proffered various methods of putting the pFET on dabs of epitaxially grown (110) silicon while keeping the nFET on (100) silicon. It was complex, involving solid phase epitaxy, multi-step integration techniques, and in most cases silicon-on-insulator (SOI) substrates.
HOT pursued higher (110) hole mobility, squeezing more performance out of the pFET while keeping the nFET roughly the same on the (100) silicon.
Parallel to this effort, researchers such as Dimitri Antoniadis, an expert in process modeling at the Massachusetts Institute of Technology, began talking about channel carrier velocity as a key metric, supplanting mobility. At a 2006 International Electron Devices Meeting (IEDM) short course on 32 nm CMOS technology, Antoniadis said that velocity would not change from the 45 nm generation onward. Velocity, he predicted, would peak at 1.65 (107 cm/s) and remain there for the 32, 22, and 15 nm generations. Antoniadis took aim at several industry assumptions that memorable Sunday in San Francisco, and concluded that shrinking the gate length no longer would lead to automatic performance gains.
Scott Thompson, the University of Florida professor who worked at Intel from 1992-2004, agrees that at sub-100 nm gate lengths, mobility becomes a less meaningful concept.
“Mobility is a long-channel parameter, defined as the speed if the carrier is going 10 μm. If the carrier is traveling 10 nm, the concept of mobility breaks down, which is why many people are confused,” Thompson said.
In long-channel devices, technologists seeking to calculate performance would multiply the mobility by the effective mass of the carrier. “That whole concept breaks down at these device dimensions. We need to rethink the starting point of a small device, and it is not necessarily high mobility.”
In nanometer-scale devices, electrons and holes don’t scatter as much as they did within larger devices, he said, adding that mobility measurements depend on scattering.
With Antoniadis and others putting the spotlight on velocity saturation as a key metric, Thompson started thinking harder about IBM’s HOT work. He postulated that if velocity saturation was the key limiter, nFETs should perform just as well in (110) silicon as in (100) silicon. He set to work with Rusty Harris, an AMD assignee at Sematech, to test out the theory. Thus far, the answer appears to be yes.
“Independent of the voltage, independent of the mobility, the nFET velocity is the same for the both the (100) and (110) orientations. That’s what you would expect from the band structure, the same maximum velocity,” Thompson said.
This is a conceptual breakthrough akin to the realization that since light bends when going through water, that would be a good thing for lithography, or the insight that uniaxial strained silicon produces a lighter effective mass, which would be a good thing for pFET performance.
It is too early to say that any big part of the chip industry will switch to (110) silicon, which appears to provide a 15% performance boost over (100) CMOS without additional costs. But just as the auto industry flipped from rear wheel drive to front wheel drive for better road stability, the chip industry could switch to (110) silicon to take advantage of the higher pFET performance, particularly in low cost ICs.
This work is a confluence of modeling -- where simulation skills and insights in the field of device physics converge – and the experimental, practical pursuit of higher transistor speed at low costs.
Already, pFETs are benefiting from strain techniques in (100) silicon, getting bigger boosts than the nFETs.
The design implications are major. If the pFET could be made to operate at parity with the nFET – as Rusty Harris’ work at Sematech shows for 80 nm devices in (110) silicon – then circuit design techniques would be altered.
As Intel research manager Paul Packen pointed out, at the 2007 IEDM short course on CMOS scaling, NAND gates are now favored because the nFETs, which favor NAND gates, run faster than the pFETs. “As the pFET gets stronger, the NOR gates get better. That is the kind of thing that circuit designers take into account,” Packen said in his IEDM lecture.
Posted by David Lammers on January 28, 2008 | Comments (4)
