Hutcheson: 2025 Likely Date for 450 mm

Alexander E. Braun, Senior Editor -- Semiconductor International, 1/16/2008 9:05:00 AM

The 450 mm wafer generation is unlikely to occur over the next dozen years, with 2025 as the “likely date” that the larger wafers will come into use, said Dan Hutcheson, CEO of market research firm VLSI Research Inc. (Santa Clara, Calif.).

An overbearing emphasis on costs is spreading throughout the chip industry, keeping fabless design teams at the trailing edge, suppressing investments by the foundries, and pushing back the wafer size transition, Hutcheson said Tuesday in a presentation at the SEMI Industry Strategy Symposium (ISS), being held this week in Half Moon Bay, Calif.

“Our analysis indicates that it’s [450 mm] probably going to happen in the 2020s,” Hutcheson said, adding that his company did an Internet-based survey, combined it with other VLSI research, and “came up with 2025 as a likely date.”

“I’ve never believed that 2012 was a viable date. If we’re smarter than we were with 300 mm, we might bring it in around 2020-2025. It’ll come faster if those who want 450 mm wafers belly up to the bar and spend some money.”

Referring to a plan to establish a 450 mm wafer handling test bed at the International Sematech Manufacturing Initiative (ISMI, Austin, Texas), Hutcheson said, “It’s encouraging that some research is being done on handling issues without waiting for the crystal pullers.”

The transition to 450 mm wafers may be delayed by weak investments. To see a larger version of this chart, click here. (Source: VLSI Research Inc.)

Fabless boom at an end?

Hutcheson said far-reaching changes are taking place among foundries and the fabless IC companies. In recent years, Hutcheson has argued that the fabless-foundry model has lost its ability to remain at the leading edge of process technology. That controversial argument takes on importance as several major integrated device manufacturers (IDMs) — under pressure from Wall Street and private equity investors — moved a portion of technology development and manufacturing to the major foundries in 2007.

“Capital costs drive changes in the supply chain,” Hutcheson said, arguing that foundries have struggled in recent years as their capital costs have increased.

With fabless design teams avoiding sub-100 nm designs, foundries are “buying all the 200 mm memory equipment that they can to avoid spending on new 300 mm tools.”

The sub-prime mortgage crisis and the drying up of capital markets, he said, have also complicated things for the foundries and other capital-intensive parts of the industry.

Arguing that Texas Instruments Inc. (TI, Dallas) has made a decision “to get off the technology treadmill and go fabless,” Hutcheson said TI will come to regret its decision to rely more heavily on foundries, given the foundries’ problems in staying at the leading edge. “Some view [TI’s decision] as the beginning of the trend to go fabless; I believe that it’s the end. The most powerful companies shift last, not first,” Hutcheson said.

Companies such as Qualcomm Inc. (San Diego) and Xilinx Inc. (San Jose) were leaders in moving to foundries. Hutcheson said foundries are now having a difficult time keeping up with leading-edge processes. “R&D costs are hammering them, and they cannot crack the <100 nm yield challenge because they lack development capabilities,” Hutcheson said.

In part, the foundries are limited by the relatively weak R&D spending by the equipment companies. “For the first time in the industry’s history, equipment manufacturers have been spending less on R&D, as a percentage of sales, than the rest of the semiconductor industry,” he said. “That means foundries can no longer get their process technology for free when buying tools.”

A core challenge facing the fabless-foundry model is found in the evolution of design. “EDA has caused a huge shift in the supply chain,” Hutcheson said. While designers earlier had to be aware of process technology, he said design complexity has caused an overly sharp separation between process and design.

Design costs are limiting the move to <100 nm designs. (Source: VLSI Research Inc.)

Also, too many small fabless companies are avoiding leading-edge processes, staying above the 100 nm inflection point where design costs can increase sharply. “The economics of design is stacking up against the small designers,” he said. “A coping strategy has been to avoid the nanochip region, to remain above 100 nm,” he said.

IDMs getting stronger?

Fabless companies are less interested in differentiation, he said. “When you talk to a foundry CEO, he says that all that the fabless guys are interested in is cost. Then any test equipment supplier selling to the fabless companies will tell you his customers don’t talk about technology enablement, but about keeping costs down.”

Hutcheson argued that the IDMs are making a comeback “because capital spending draws market share. If you spend at a 10-20% sustaining rate, you keep your market share. Spend more and it grows. In the 1990s, foundries outspent IDMs and the IDMs lost. The reverse is taking place now.”

Companies that invest in integrated manufacturing capacity have enjoyed higher sales in recent years. (Source: VLSI Research Inc.)