IITC Gives Glimpse of Future Interconnect
Alexander E. Braun, Senior Editor -- Semiconductor International, 6/2/2008 7:55:00 AM
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This year, the conference boasts a session on 3-D, reflecting the increasing work being done in this area by device makers. 3-D is important for performance because the average line length tends to be long and slows down performance. By adding another dimension, lengths are decreased and performance improved. Engineers are seeing little improvements in smaller CMOS structures. As Shapiro put it, “We aren’t getting faster microprocessor clock speeds, whether for the PC, networking processors or even in mobile application devices. Clock speeds are not increasing as before because of higher power requirements. A way around this is by putting more than one core on a piece of silicon or using different kinds of processors.”
The problem with this is that as these are added, the module’s bandwidth becomes a limiting factor. Thus, although there may be more processing power in the same space, getting the microprocessor to talk to other devices still remains a problem because the number of pins has not increased. Additional capability on the silicon does not necessarily mean better performance. The importance of 3-D lies in its capability to increase bandwidth. However, when packages are put on top of packages, or chips stacked and wire bonded, this results in heat that must be dissipated.
A paper that addresses this problem will be presented by the Georgia Institute of technology (Atlanta), titled, “A 3D-IC Technology With Integrated Microchannel Cooling,” by D. Sekar et al., IBM and Nanonexus. It will describe a technique that creates small microfluidic cooling channels between the chips (Fig. 1).
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| 1. Georgia Tech, IBM and Nanonexus researchers will describe an integrated microfluidic heat sink technology for 3-D ICs. The heat sinks are on each chip’s backside, and coolant is delivered by means of fluidic through-silicon vias (TSVs) and pipes. Deionized water is pumped through the micro-channels at a flow rate of 65 mL/min. The micro-channels and TSVs were formed in one etch step. A sacrificial polymer was used to fill and protect them while another layer was built and later decomposed to create the TSV/channel structure. (Source: Georgia Institute of Technology) |
The conference again covers beyond-CMOS issues. While nanotubes can be used with CMOS, there are issues such as how to raise the back end’s speed. A paper by Toshiba (Tokyo) and Stanford University (Palo Alto, Calif.), “Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit,” by G. Close et al., will discuss ways to integrate smaller and longer multi-strand nanotubes into the CMOS as interconnects (Fig. 2).
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| 2. First test of carbon nanotubes (CNTs) as interconnects in a real circuit. As copper lines scale down, their resistivity will eventually increase, degrading overall performance. CNTs have a lower theoretical resistivity than copper, but until now have not been used as interconnects in a real CMOS IC. A Stanford and Toshiba team will tell how they built a 0.25 µm CMOS test chip containing an array of ring oscillators. Each ring oscillator was deliberately missing an interconnect wire, which was replaced with a multi-walled carbon nanotube (MWCNT) on top of the chip. The MWCNTs were 30 nm in diameter and up to 14 µm long. Sub-nsec delays attributable to the CNTs were measured, but the actual resistance of the MWCNTs is ~150× greater than predicted, illustrating an important gap between the static resistance and dynamic behavior of MWCNTs. Section A shows an array of MWCNT interconnects; B is a close-up of an 18-μm-long individual interconnect; and C is a TEM image of a typical MWCNT interconnect with a ~30 nm outer diameter. (Source: Stanford University) |
Other papers are scheduled to describe the use of ruthenium for line material. As vias and lines shrink, their resistivity is increasingly influenced by the liner seed. When the copper shrinks, the liner seed is next to it. This used to be a small part of the metal line or via, but it is now a larger percentage. Ruthenium is a lower resistance material and two of the papers look at how to make it a better barrier. “Highly Reliable Low Resistance Cu Contact using Novel CVD Ru/TiN/Ti Stacked Liner, by M. Kitamura et al., of Toshiba will outline a process to add titanium to ruthenium to keep the copper from diffusing and getting to the dielectric. Yet another paper will show results with amorphous, instead of crystalline, ruthenium. Crystalline ruthenium has grain boundaries into which copper may quickly diffuse. Because an amorphous ruthenium film does not have any grain boundaries, it slows down copper diffusion.
Air gap techniques are slowly gaining momentum. Low-k materials are being pushed as far as they can go, hampered by their mechanical properties. Reliability has always been an issue with air gaps, with problems such as the extrusion of metal into the gap. Toshiba will describe a low-cost method to produce air gaps that use a sacrificial polymer on all eight levels of a structure, leaving it there until the end in “Cost-Effective Air Gap Interconnects by All-in-One Post Removing Process,” by N. Nakamura et al. It is then decomposed through small holes through the various levels, allowing it to flow out simultaneously instead of layer by layer.
An invited paper by Georgia Tech, “Performance Benchmarking for Graphene Nanoribbon, Carbon Nanotube, and Copper Interconnects,” by A Naeemi et al., will present a model that compares copper to graphene to carbon nanotubes and their potential impact on performance. According to Gary Ray, senior technologist in the thin film/diffusion effort at Intel Corp. (Santa Clara, Calif.) and General Co-chair of the conference’s Executive Committee, this research might set a direction for future work.
As a whole, although the papers promise to be excellent, they appear to be evolutionary, not revolutionary, in character.
IITC is truly going international, and next year will be held in Sapporo, Japan, reflecting the fact that considerable manufacturing and development is now taking place in Asia. The following year, the conference returns to the United States, with it possibly taking place in Europe the year after that. In short, the conference is following in the footsteps of the industry itself as it shifts from one part of the globe to another.
