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IMEC, Aixtron Partner on GaN Deposition

Staff -- Semiconductor International, 6/3/2008 10:48:00 AM

Researchers from IMEC (Leuven, Belgium) and Aixtron AG (Aachen, Germany) said they have demonstrated the growth of uniform AlGaN/GaN heterostructures on 200 mm silicon wafers. Demand is growing for gallium nitride (GaN)-based solid-state switching devices, but costs are an issue. GaN heterostructures are grown on expensive sapphire and silicon carbide (SiC) substrates now, and the ability to use the larger 200 mm silicon substrates will lead to lower-cost GaN power devices, the partners said.

The thickness uniformity map of a 1 µm GaN layer deposited on a 200 mm Si (111) substrate using an AlN/AlGaN buffer. The average thickness measured in situ is 1008 nm for the full wafer excluding a 5 mm edge.
The thickness uniformity map of a 1 µm GaN layer deposited on a 200 mm Si (111) substrate using an AlN/AlGaN buffer. The average thickness measured in situ is 1008 nm for the full wafer excluding a 5 mm edge.
The process was demonstrated at the Aixtron application laboratory using the company’s 300 mm Crius metal organic chemical vapor phase epitaxy (MOVPE) reactor. The 200 mm silicon (111) wafers were developed by MEMC Electronic Materials Inc. (St. Peters, Mo.) using the Czochralski growth method suited to switching applications with large breakdown voltages.

Marianne Germain, program manager of IMEC's Efficient Power program, said the layers show good crystalline quality as measured by high-resolution X-ray diffraction (HR-XRD). "The demonstration of GaN growth on 200 mm silicon wafers is an important step toward processing GaN devices on large silicon wafers," she said.

An aluminum nitride (AlN) layer was deposited on the silicon substrate, followed by an AlGaN buffer that provides compressive stress in the 1-µm-thick GaN top layer. The stack was finished with a 20-nm-thin AlGaN layer and capped with a 2 nm GaN layer. From in situ measurements, the researchers were able to extract the thickness uniformity of the different layers, which show a standard deviation <1% over the full 200 mm wafers.

However, Germain said the bow of the wafers is still quite large, in the range of 100 µm, which can be solved by an optimized buffer. "We aim to further develop the growth process and to qualify the wafers to be compatible with a silicon CMOS process."

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