IITC Papers Range From Plasma Modeling to Copper Encapsulation Techniques
Alexander E. Braun, Senior Editor -- Semiconductor International, 6/4/2008 7:51:00 AM
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In an invited paper, “Progress, Opportunities and Challenges in Modeling of Plasma Etching,” Y. Yang, M. Wang and M. Kushner of Iowa State University (Ames) observed how plasma etching process equipment development is hampered by the chemistries’ complexity and plasma tool performance unpredictability, sometimes resulting from design differences. The authors addressed challenges associated with modeling physical vapor deposition (PVD), plasma deposition, plasma etching and ion implantation processes.
“Modeling has produced quantifiable improvements in the development cycle of these tools, as well as providing more qualitative improvements in the understanding of the plasma transport and the chemistry occurring in the tools; however, modeling and simulation still face significant challenges,” Kushner said (Fig. 1). These include the introduction of unfamiliar materials such as high-k dielectrics, which increase the dynamic range of operating conditions in very high-frequency plasma sources, something beyond the realm of established modeling techniques. “Manufacturing issues requiring extreme spatial resolution must be solved,” he said. Addressing these hurdles will require improvements in the knowledge of material properties for plasma transport — cross-sections and transport coefficients, for instance — but, more importantly, for the plasma surface interactions that result in feature evolution.
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| 1. Modeling of very high-frequency RIE plasma tools. Schematic showing the location of the RF power feed and intervening materials (a). Plasma density for 10 MHz, argon, 50 mTorr and 300 W. Maximum density is noted (b). Density for 160 MHz (c). (Source: Iowa State University) |
Problems in improving process development by modeling will be met when plasma and profile models are adaptive, self-aware and self-correcting in changing reactor conditions. Models that automatically generate their own reaction mechanisms and reaction rate coefficients, and have access to databases that are automatically queried, will lead the industry in advanced plasma etching chemistry development.
A plasma-enhanced atomic layer deposition (PEALD)-grown mixed-phase/nanolaminate barrier that combines TaN’s robust barrier properties with direct-plate characteristics of ruthenium was the subject of “ALD Growth of a Mixed-Phase Novel Barrier for Seedless Copper,” by S. Kumar et al. of the University at Albany-SUNY. It was observed that a mixed-phase barrier as thin as 2-5 nm can act as a robust copper barrier and direct-plating layer by modulating the ruthenium:tantalum ratio in the deposited films. The filling characteristics in <50 nm features are equivalent to those of conventionally copper-seeded interconnect structures.
Traditional interconnect uses a complex, thick, tri-layer configuration (copper seed/glue/barrier layer) before deposition. Because of PVD’s intrinsic drawbacks, this can present scalability issues for future interconnect geometries requiring a continuous and ultrathin (<5 nm) diffusion barrier. A robust single-layer diffusion barrier with intrinsic copper direct plate and adhesion characteristics not needing an additional copper nucleation/glue and seed layer is desirable. To avoid intrinsic conformality shortcomings associated with PVD, an ALD barrier deposition approach seems promising for emerging dual damascene structures.
Materials such as ruthenium, platinum and iridium have been investigated as potential direct-plate materials; however, because of microstructural issues, these do not provide a robust copper diffusion barrier. TaN and TaSiN are inappropriate for direct plating because of surface chemistry characteristics. A potential solution uses a bilayer configuration, such as ALD TaN/ALD ruthenium, to enable both barrier and plate/adhesive properties. However, a bilayer stack is not downscalable to smaller thickness because the individual layers are anticipated to require a thickness of several nanometers for each to serve their individual functions. A mixed-phase monolithic diffusion barrier — scalable to a smaller thickness while still possessing adequate functionality to serve as a direct-plate diffusion barrier — is desirable.
The PEALD process produced a mixed-phase Ru-TaN barrier with ruthenium:tantalum ratio of 12 with excellent copper diffusion barrier and direct-plate characteristics, without a separate adhesion/glue and a copper seed layer (Fig. 2). The direct-plate ALD alloy liner seems scalable to smaller thicknesses, offering an alternative for high-performance copper metallization extendibility.
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| 2. SEM cross-section of patterned SiO2 trench structures with 35-250 nm linewidth, coated with a ~5 nm Ru-TaN liner followed by ECD copper, both with (bottom) and without (top) the use of a separate seed layer. (Source: University of Albany-SUNY) |
“Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond,” by H. Kudo et al. of Fujitsu Laboratories Ltd. (Tokyo) focused on how a self-aligned barrier technique was applied to copper wiring encapsulated with a MnO barrier to further enhance electromigration resistance. The self-aligned barrier and encapsulation techniques increased maximum current density to nine times that of the traditional one. The copper wiring, fabricated by the combination of the two techniques, also had greater resistance to stress-induced voiding set off by thermal stress. This enhanced the lifetime of time-dependent dielectric breakdown (TDDB) by a factor of 160.
Advanced LSIs need higher transistor drive current than conventional ones — up to 2 mA per NMOS transistor in the 32 nm node. A high drive current also requires higher maximum current density (Jmax) in copper wiring. Thus, electromigration resistance must be considerable increased. A copper wiring encapsulation technique based on the process of a self-formed MnO barrier produces high electromigration resistance without degrading stress-induced voiding resistance. The CuSiN barrier, formed on top of the copper wiring using a self-aligned barrier technique, also has the potential to increase electromigration resistance. To further enhance this resistance, the authors combined encapsulated copper wiring with the self-aligned barrier technique, focusing the 32 nm node and beyond.
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| 3. Sequence depicting the self-aligned barrier and copper wiring encapsulation. (Source: Fujitsu) |
Copper wiring electromigration resistance was greatly enhanced with a combination of copper wiring encapsulation and self-aligned barrier techniques. Jmax increased by a factor of nine. Applying the self-aligned CuSiN barrier to the encapsulated copper wiring increased resistance to stress-induced voiding failure set off by thermal stress. In contrast, the control sample, which had a very thin barrier, equivalent to that for the 32 nm node technology, applied to the CuSiN’s self-aligned barrier was seriously degraded by thermal stressing.
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