Yield Goals for 22 nm

Semiconductor manufacturers are facing many defect, film and lithography metrology issues in the move to 32 nm dimensions. The optical defect inspection tools do not adequately detect defects at 45 nm, while scanning electron microscopes (SEMs) are too slow. With each successive technology node, critical dimension (CD) metrology measurements become more difficult because CD-SEM and optical CD (OCD) measurement capability is being reached. In addition, new overlay methodologies are required to replace traditional box-in-box overlay targets, which lack the accuracy required in the device patterning process.

Defect, films and lithography metrology projects by the International Sematech Manufacturing Initiative (ISMI) are aimed at accessing and improving the manufacturing worthiness of measurement equipment. The first step toward determining manufacturing worthiness is creating a standardized set of test wafers. We then evaluate the latest production and development tools using these test wafers and create consensus criteria or specifications based largely on the International Technology Roadmap for Semiconductors (ITRS) requirements. Next, we model the limits of currently available technology to project the furthest sensitivity and usefulness of the tools.

Defect metrology

Brightfield and darkfield optical tools are the most widely used systems for defect detection. However, SEM-based systems are increasingly being used, offering greater resolution. But while its 1 nm electron wavelength is shorter than visible light, SEM detection is hampered by slow scanning speeds — a problem that is exacerbated by growing wafer sizes. Furthermore, SEM analysis is conducted in a vacuum environment where the reliability of the chambers containing the columns is considerably less than that of optically illuminated systems.

As design rules shrink, the wave properties of the visible and near-visible light deployed in both brightfield and darkfield systems interact with device layouts as if the layouts were diffraction gratings rather than distinct features. Reflectance lobing from structures that were previously resolved as straight edges imposes resolution and noise issues that are difficult to overcome, impeding the tool's ability to differentiate between signals from defects of interest and nuisance defects.¹

The Yield Enhancement chapter of the ITRS states that improved resolution down to a 0.5X feature size is required for inline defect detection (Table 1).² Detection of very small defects on both patterned and unpatterned wafers at the 32 nm node and below is of particular concern. High-aspect-ratio inspection (HARI) is one of the key issues for interconnect defect control. As device margins become narrower, contact resistance failure caused by slight residue remaining on the bottom of contact is becoming a distinction problem, separate from whether the contact is physically open or not.

Possible solutions

The International Sematech Manufacturing Initiative (ISMI) Defect Metrology program addresses many of the challenges facing yield and defect metrology. It also coordinates the Defect Metrology Advisory Group (DMAG), where technologists and managers from 16 member companies meet and consensus is built to define the strategic roadmap. Unified specifications are defined that describe the requirements for future-generation defect metrology tools. Wafer standards are developed to check the performance of current and developing metrology tools. These standards are directed at examining tool sensitivity and repeatability for the current half-pitch node and the next two future nodes. Currently, this would include 45, 32 and 22 nm. Major thrust areas within the Defect Metrology program include inspection of patterned and unpatterned wafers, and on bevel edges.

Patterned wafer inspection — Intentional defect arrays (IDAs) are used as wafer standards for patterned wafer defect inspection platforms. The standards are constructed using typical SRAM and logic layouts for the designated node. To test the sensitivity of tools, intentional defects are patterned into the layouts in sizes ranging from 25% to 400% of the half-pitch. They are 14 different defect types, including shorts, feature extensions and feature intrusions.³

Testing done using the IDAs show the limits of detection for each type of defect, allowing the vendor to understand where the structure of the platform works and where it does not. Example defects are shown in the Figure.

Intentional defects to test detection and review tools. An 18 nm bridging defect structure in the Y direction (left) and a 16 nm edge intrusion in the X direction (right) in a 65 nm MI trench.

The current IDA design focuses on 2-D defects for gate and metal trench structures. The development of contact standards for the theoretical study and feasibility test on HARI structures using various inspection systems has been proposed. The generation of standard samples for general-purpose contact evaluation is currently under consideration to extend the role of metrology.

Unpatterned wafer inspection — Although there have been some improvements made in the defect detection sensitivity by introducing a shorter wavelength laser and optimized optics, they do not meet the sub-45 nm ITRS requirements. According to the product development plans from toolmakers, shorter wavelength systems will be introduced in the next few years to achieve higher sensitivity. In the meantime, chipmakers will have to extend the use of current tools by optimizing their performance to meet their needs.

Particles that are of concern to the process are different from the polystyrene latex spheres (PSLs) and show different sizing effects. One possible solution is to transition from PSLs to using natural particles in the examination of unpatterned wafers. Process particles like silicon and tungsten have higher refractive indices than PSL materials, often resulting in larger sizing from the scanner system. Process particles also reflect the real challenges of unpatterned inspection better than PSLs; real particle defects are often decorated with or embedded into the film material, presenting complications that process particles can replicate better than PSLs. The main obstacle to using process particles, however, is traceability of particle size, which is extremely well quantified with PSLs. ISMI is currently investigating the traceability of various natural particle sources to evaluate their potential use in unpatterned wafer inspection.

Haze on the wafer surface is a significant obstacle to sensitivity. However, in a manufacturing environment, except for incoming inspection, there is limited ability to use prime bare wafers for process monitoring. Engineering bare wafers usually have higher haze levels than product grade wafers, which needs to be taken into account when developing defect monitoring methodologies.

Monitoring haze for process control poses another challenge of unpatterned inspection systems. Using a scattered light (i.e., haze) measurement from the surface of the wafer as a proxy metrology has recently been introduced. Some published reports indicate good utilization of the tool as a process monitoring system, with high throughput and potential use as a proxy metrology. However, the development of haze standardization with regard to the intrinsic property of the roughness measurement data is important for the system to be categorized as an inline metrology system. The generation of standard samples for general-purpose haze measurement is currently under consideration at ISMI.

Bevel/edge inspection — The introduction of immersion lithography, integration challenges of new advanced materials, thinner layers, and an increased need to recover edge surface area on larger wafers have made bevel/edge inspection for pattern wafers the top priority in yield enhancement.

Bevel/edge inspection tools were originally used by silicon wafer manufacturers for monitoring and controlling the formation of the bevel profile on bare silicon wafers. As the need for inspecting bevel/edge on pattern wafers grew, inspection technologies evolved to address higher sensitivity, surface noise suppression and multiple illumination and detection setups to cover different defect types. There remain several technical challenges related to wafer-edge inspection on pattern wafers that do not have satisfactory solutions with the current technologies in the areas of detection sensitivity, automatic defect classification (ADC) and nuisance filtering, imaging resolution and review, and accurate reporting of defect location that is essential for SEM review.

In the area of SEM review, although some recent improvements have been made, the capabilities for reviewing wafer-edge defects also need to be expanded, such as coverage of the lower bevel-edge zones, automatic defect offset and ADC. Because of these challenges in both inspection and review, bevel/edge inspection tools have not yet been widely adopted by chip manufacturers for inline inspection as part of overall yield enhancement methodologies. In addition, defect management systems (DMS) are yet to expand data collection of bevel-edge defects, include analysis and display features similar to those available for wafer surface defects, integrating the bevel-edge zones as a contiguous part of the wafer surface. In this area, ISMI helped by defining a new E30.¹ SEMI standard to include zone and Z information, and started working with DMS providers to integrate bevel-edge information and analysis to current platforms.

The delay in the adoption of bevel/edge inspection tools may also partially be the result of the lack of wafer standards. Wafer standards need to be developed for testing bevel/edge inspection tool performance to meet ITRS requirements. ISMI has started working on generating wafer standards that will help develop benchmarks for equipment suppliers and serve as performance targets for evaluation, qualification and tool monitoring.

ISMI is revisiting a study conducted in 2005 to isolate the sources of errors that cause false defects during review. Specifications will be developed and results will be communicated to suppliers of defect inspection and review equipment to improve automated defect review. Finally, ISMI coordinates Yield Council meetings, where yield managers from 16 member companies meet to share best-known methods.

Thin-film metrology

Film metrology has become an increasingly broad area in semiconductor manufacturing, encountering new challenges as different approaches are undertaken to improve device performance. New strategies, such as the incorporation of strain to improve carrier mobility, reduced device geometries that require shallower and more abrupt implants to improve transistor control, and advanced gate structures and materials to reduce leakage current have created a new set of thin-film measurement challenges.

An increased need for advanced process control (APC) has also placed more demand on inline metrology. ISMI is currently undertaking a number of film metrology projects related to thin films, strain, ultrashallow junction, active dopant, workfunction and dielectric damage metrology. Each of these areas will require test structures and reference metrology to evaluate the performance of current tools. In some areas, such as workfunction metrology, there are currently no inline solutions.

ISMI is also engaging with tool suppliers to develop new metrology solutions, such as applications of conductive carbon nanotubes (CNTs) to scanning probe microscopy, and photo reflectance to strain and active dopant metrology. These new techniques have the potential to improve inline metrology by increasing sensitivity or throughput, thereby increasing the return on investment (ROI).

Lithography metrology

With shrinking on-chip CDs, especially gate widths and contact-hole diameters, state-of-the-art CD metrology tools have had difficulty keeping pace with the stringent lithographic and etch CD measurement requirements in cutting-edge device fabrication facilities. The tight CD and overlay control requirements for 32 nm technology and beyond appear in the ITRS Table 2.2. A 3σ metrology of <0.2 nm uncertainty will be needed for the 32 nm node in 2013. As with previous technology generations, the industry will likely achieve that node well before the target date, and there will be a need for metrology tools to meet these requirements a few years earlier because of the need for proper characterization to be available for process development activities.²

Two well-known technologies are used to perform lithography metrology: CD-SEM and optical scatterometry (also known as OCD), both of which have found their way into volume production.

CD-SEM

CD-SEM has been the traditional CD metrology of choice for many years, and its use will continue. CD-SEMs are imaging microscopes that map a target with a focused, rastered electron beam (e-beam).

The ISMI Advanced Litho Metrology Advisory Group (AMAG) meets twice a year to write and maintain "Unified Specifications" for CD-SEMs. Methodologies and metrics have been formulated for the demands of the 32 nm technology node and beyond. ISMI's CD evaluation project has been ongoing to periodically evaluate how well the suppliers' tools have kept pace with the needs of their customer base. These consensus data sets have yielded many tactical and strategic benefits over the years to member companies, and have also greatly aided the tool suppliers in feedback for product improvements.

Major issues for future attention should include further improvement of CD matching, ArF resist shrinkage, contact hole imaging, navigation matching between tools, accuracy, and roughness measurement (including line-edge roughness [LER] and linewidth roughness {LWR]). CD-SEMs are effective tools for measuring LWR and meet current ITRS needs, and standardization of measurement techniques and calibration across the industry has been greatly improved because of the new LER measurement SEMI standard.⁴

ISMI has collaborated with the National Institute of Standards and Technology (NIST, Gaithersburg, Md.) to look into CD-SEM extendibility, and currently concluded that there are, at present, no real show-stoppers for CD-SEM into the 22 nm node, with partial visibility into the 18 nm node. Another major AMAG project to better understand ArF photoresist shrinkage was recently completed. Extrapolation to original, pre-shrink CD from the CD results of several consecutive measurements seems feasible. Shrinkage becomes smaller but faster in smaller features, such as those achieved with near-future immersion lithography. This is because of the fact that the features are becoming as small as the e-beam interaction volume of the SEM, so that all resist material is shrunk simultaneously instead of from the outside in, as with larger features.

Recent CD-SEMs can measure multiple features within the same image without appreciably affecting speed, enabling the measurement of local process averages and variances. This feature improves the CD-SEM's ability to perform process control and characterization.

For the near future, AMAG has determined that there are no major limitations for CD-SEM into the 22 nm node, with partial visibility into the 18 nm node. In immersion lithography, ArF photoresist shrinkage becomes less and occurs faster in smaller features. The features are becoming as small as the e-beam interaction volume of the SEM, so that all resist material is simultaneously shrunk, removing variation from multiple testing.

Optical scatterometry

Scatterometery (OCD) tools are variations of the spectral ellipsometers and reflectometers used for CD metrology. They function by collecting the spectra of reflected photons from a grating target.

AMAG maintains an OCD Unified Specification, which owes much of its structure and many of its metrics to its aforementioned CD-SEM cousin. A rigorous OCD tool evaluation regimen is also active. Results have shown a capability of tooling for 32 nm node gates with sensitivity to profile metrics, such as sidewall angle and height. Contact holes of dense pitches are also measurable. Best 3σ precisions seen are in the 0.1 nm range with ~1 nm accuracy. As for speed, one tool tested met the long-sought 1 sec move acquire measure (MAM) time, although many scatterometers are much slower in spite of advertised claims. No resist shrinkage problem has been observed, as in the case of SEMs, although some resists may exhibit bleaching after ultraviolet (UV) exposure, large doses of which change n and k values. Tests also show that OCD tools' beam spot size ranges from 20 to 60 μm. Because precision improves with larger beam spot sizes, there is an advantage to measuring more features with the larger spot. However, chip manufacturers are pushing for smaller spot sizes and grating targets for improved real estate because smaller gratings might fit inside the region of a circuit, making OCD measurements more representative and meaningful for process control.

AMAG also funds an OCD extendibility study with NIST, where simulations of features in future ITRS technology nodes, such as metal gates, are done to show OCD capabilities into the future. Basic results show that there are, at this time, no real show-stoppers for OCD utility into the 22 nm node. Further work is being done to look at the 18 nm node and beyond. However, questions remain about how OCD will perform with double patterned (DP) features, since these will include bimodal distributions of CD, pitch, sidewall angle and height. In some DP schemes, adjacent lines will exhibit different n and k. Over-parameterization might become an issue. Also, materials where n and k have a tendency to shift over time can be an issue in manufacturing, and this issue may get worse in future technology nodes.

Overlay metrology

In its investigation of overlay technology, ISMI has reviewed the performance of many different technologies, all of which can potentially meet ITRS requirements for metrology precision through the 32 nm technology node, but fail to directly measure in-device structures. Previously, Sematech (Austin, Texas) and KLA-Tencor (San Jose) have shown that traditional box-in-box overlay targets display significant inherent instability in the purpose-built overlay metrology target when the metrology system is highly stable.

The move from traditional box-in-box targets to periodic, or grating-type, structures has led to better measurement precision. State-of-the-art overlay measurement systems can now perform in the 0.2 nm precision range, which is more than adequate to meet precision requirements down to the 32 nm node.

As important as measurement precision is the ability of the overlay measurement to predict in-device overlay. Also, the overlay measurement mark must be resistant to wafer processing variations and should experience the same scanner/lens-induced pattern-placement shift as design rule structures in the device. One measure of the prediction accuracy of an overlay measurement structure is to compute the post-modeled measurement residuals that are left after all of the exposure system correctable terms are removed. The most recent grating structures introduced in 2008 have shown a reduction of field-to-field modeled residuals down to the 3–4 nm range. However, new DP litho exposure schemes will require a total overlay budget of this same 3–4 nm. These measurement residuals must be further examined to allow for the device to be within the overlay requirements set forth by DP lithography processes.

Another component of the prediction accuracy of an overlay metrology structure involves the pattern-placement shift or error that is associated with the lithographic exposure system. It has been shown that different device feature sizes experience different lateral translations at the wafer plane. Initial grating style overlay metrology structures were optimized by minimizing the metrology precision error. This resulted in gratings that were larger than design rule features. However, because of their large feature sizes, these structures did not experience the same lateral translation at the wafer plane as design rule device features do. Newer grating structures are moving closer to design rule sizes to address this issue.

ISMI continues efforts to ensure capable overlay metrology for the 32 nm technology node and beyond. Test structures have been designed in 2007/2008 that will allow for the investigation of several overlay metrology technologies. Tests are planned to examine the issues with target sizing and overlay accuracy. These designs are included in a fifth-generation metrology test reticle, based on alternating phase-shift reticle technology, that will be completed in the summer of 2008. These structures and reticles, which will be used to test current and next-generation overlay metrology technologies to ensure that they are capable at the 32 nm node, will be delivered to ISMI member companies to be tested and fine-tuned.

Next-generation overlay metrology efforts also include small-target in-device measurements and optics improvements to measure these targets, diffraction-based measurements, and secondary electron-based overlay measurements. Finally, work is proceeding on an overlay reference measurement system to enable highly accurate measurements of actual in-device overlays.

Summary

ISMI's Defect Metrology program consists of projects in the areas of defect, films and lithography metrology. Its assessments have shown that a number of major gaps must be addressed in next-generation defect detection equipment. It has also shown that CD metrology equipment can meet the requirements of the 45 nm nodes, with projected success into the 22 nm node. However, overlay metrology still requires new target structures. ISMI will continue to evaluate the manufacturability of defect detection and review, films, CD and overlay metrology equipment.