Mentor reorgs to better approach sub-45-nm design

The assets that Mentor recently acquired from Ponte Solutions and NXP Semiconductors Germany DFT technology further augment the resources of the division in order to drive the integration of its three main platforms based on a common vision for delivering first-pass silicon success, the company noted.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 6/10/2008

Semiconductor design software provider Mentor Graphics Corp Monday detailed its IC implementation strategy that first involves merging several product areas into a single design to silicon division, namely the Calibre physical verification and design for manufacturing (DFM) platform, the Olympus-SoC place-and-route system (from the Sierra Design Automation acquisition), and Mentor’s design-for-test and yield learning tools. The company said it is doing so to help customers with the challenges of moving to smaller process nodes.

The assets that Mentor recently acquired from Ponte Solutions and NXP Semiconductors Germany DFT technology further augment the resources of the division in order to drive the integration of its three main platforms based on a common vision for delivering first-pass silicon success, the company noted.

“We are aligned with customers in our vision of how to meet future challenges, and have a strong technology roadmap to deliver new capabilities through platform advancements and cross-platform integration," Joseph Sawicki, VP and general manager of Mentor’s design to silicon division, commented in a statement. "We’re engaged with our customers on a day-to-day basis in their design labs and fabs to ensure the Mentor offerings truly resolve customer needs at each step.”

Further, Philippe Magarshack, STMicroelectronics’ technology R&D group VP and central CAD and design solutions general manager, noted that ST has collaborated with Mentor for many years to address IC implementation challenges at each successive technology node. “We were also working with Sierra Design Automation before the acquisition by Mentor, and we encouraged the integration of Olympus-SOC and Calibre technologies to address the increasing challenges we foresee at 32/22-nm. We believe the Mentor solution will help us meet critical IC implementation challenges such as the complexity of multi-mode, low power designs, designing for high manufacturing yields, and achieving market-leading performance.”

Platform capabilities discussed at the Design Automation Conference being held this week in Anaheim, Calif. include the Equation-based DRC facility of the Calibre nmDRC platform, which allows users to easily implement advanced multi-dimensional (2D/3D) physical verification (PV) checks that are difficult, if not outright impossible, to perform today with other offerings. In addition, a new distributed computing implementation of the nmDRC platform that significantly reduces memory requirements while at the same time improving runtime, along with incremental verification features that allow multiple design rule checking runs to execute in parallel, and a CMPAnalyzer planarity solution that optimizes metal fill for best performance using both CMP models and layout density analysis.

Also, Mentor is showing a Calibre nmLVS tool with interactive debugging features (to be released to the general market in the second half of 2008) that will speed layout-versus-schematic checking with automated suggestions for fixing the design, improved short identification, and overall improvements to the environment to reduce debugging time.

Further, Mentor outlined plans for integration across its three major IC implementation platforms.

The Olympus-SoC/Calibre LFD (litho-friendly design) solution for avoidance of litho hotspots during routing will be extended with further integration of Calibre models early in the floorplanning and routing process. Concurrent multi-corner multi-mode optimization with Calibre DFM models aim to allow the Olympus-SoC product to create DFM-optimized designs in a single pass, to reduce the time required to reach tapeout, while at the same time allowing designers to immediately see the impact on manufacturability, timing, power, signal integrity and other chip performance factors.

Finally, Mentor said DFT integration with physical analysis currently provides targeted test generation for specific DFM hotspots using the TestKompress ATPG solution. Integration between physical analysis and the YieldAssist product allows direct viewing of suspect defect locations for reduced failure analysis turnaround time.

Going forward, further integration will help customers to rapidly find the root causes of manufacturing defects by being able to quickly identify hidden systematic yield limiters by analyzing volume production test data with new software techniques. Designers can also use the results of yield learning to re-prioritize and tune their recommended design rules throughout the lifecycle of a product offering, Mentor concluded.