Lithography for the 22 nm Node
Teresa McLean, Global Expositions Marketing Manager, SEMI, San Jose, www.semi.org -- Semiconductor International, 6/6/2008
The 22 nm node, expected to be reached by leading semiconductor companies in 2011, is going to be the most challenging step ever for lithography in manufacturing. There are plenty of engineering challenges, and the opportunity to overcome these challenges with elegant solutions is driving engineers to experiment with many approaches and solutions. This year at SEMICON West, the Device Scaling TechXPOT on Tuesday, July 15, will present information on the various approaches, potential solutions and risks.
Concerns over the manufacturing readiness and cost effectiveness of next-generation lithography solutions may drive the 22 nm node to be the last step for 193 nm water immersion lithography. Such an approach may work, but it may also present the industry with design-invasive resolution enhancement techniques, forcing engineers to think about making difficult choices about electrical and manufacturing challenges to even get to manufacturing.
This session, hosted by Lars Liebmann, Distinguished Engineer, IBM (Hopewell Junction, N.Y.), will discuss the feasibility of different approaches from both a technical engineering and business perspective.
Liebmann said, “Lithographers have a long and predictable history of ‘crying wolf.’ Major doomsday scenarios have been prophesized for every technology node in the last two decades, so it is understandable that the design community is taking a ‘wait and see’ attitude toward 22 nm. The second well-established attribute of lithographers is that their predictions for manufacturing lithography solutions more than five years out are consistently wrong. To stay within the scope of reasonably accurate predictions, this panel will focus on the '22 nm node' that is targeted for manufacturing ramp by leading-edge logic manufacturers in 2011. Even though no major design dimension actually approaches 22 nm, the resolution challenges for this node will be formidable.”
He continued: “The results of the 2008 Sematech Lithography forum clearly indicate that 193 nm optical lithography is the only choice for 22 nm. Even after reaching very deep into the bag of tricks for resolution enhancement techniques, patterning will occur uncomfortably close to the fundamental physical limits of optical lithography. Expert opinion on what these optical lithography tricks are, how feasible they appear, and what they will do to manufacturing profitability will open this panel discussion. To get a better understanding of ‘plan B’ — the ‘wait until an exposure process with sufficient resolution is developed’ approach — we will hear from extreme ultraviolet industry expert, Bruno LaFontain of AMD, on the demonstrated capabilities and remaining challenges of this next-generation lithography solution. For companies that cannot afford to stray from the two-year roadmap, not much more than unidirectional fixed-pitch gratings are expected to be resolvable, making the usual discussion on potential impact to conventional design scaling seem completely ridiculous. To give a sense for the feasibility of enabling an entire technology node with ultrarestricted designs, Professor Larry Pileggi of Carnegie Mellon University and PDF Solutions will share his insights gained from many years of working on highly regularized layout fabrics in an academic and industry setting. Of course, when we think of ‘design impact’ we usually think of a designer pushing back on overly restrictive design rules, but perhaps the bigger impact is to the whole physical design infrastructure. Richard Brashears of Cadence Design Systems has been at the forefront of developing manufacturability-aware design solutions, and will share his insights on the industry’s aggressive plans to work miracles in the EDA space. To drive home the message that we are not discussing an academic experiment but a practical solution suitable for high-volume manufacturing, Burn Lin, who has been a key contributor to every major lithography innovation and who is now directing TSMC’s patterning strategy, will share his thoughts on where the industry will go for 22 nm. This panel discussion provides the audience with invaluable access to industry experts from every aspect of the 22 nm design to patterning flow.
“This panel discussion is going to be a tremendous opportunity to hear from and to question the experts on detailed issues. Will there be severe layout restrictions on engineers in order to even use 22 nm designs? Will the effort to get to 22 nm cost the industry more than it’s worth? And, of course, how can the entire industry prepare for an uncertain future? Lithography has driven productivity improvements in semiconductors for a long time. No one wants to see that end. The unique opportunity to ask these senior technologists tough questions should not be missed.”
The “Lithography for the 22 nm Node” session will be held on Tuesday, July 15, from 3 to 5:30 p.m. in the North Hall.
