CD Metrology Confidently Looks Beyond 32 nm

In the relentless evolution from small node to smaller node, some of metrology's traditional standbys seem to be, if not running out of steam, beginning to redline insofar as their inspection, measurement and test capabilities are concerned. However, research and workarounds are proceeding at warp speed and, at least for another two nodes, it seems device makers' requirements will be met.

1. OCD platforms will continue to deliver the measurements that make a continued evolution from node to smaller node possible. (Source: KLA-Tencor)

McMillan underscored that a CD-SEM cannot effectively measure things like gate multi-spacer width nor perform depth measurements, such as shallow trench isolation (STI) etch depth. As device makers transition to 45 nm, logic manufacturers are using strain pockets, where they etch around the gate and fill it with silicon germanium (SiGe) to strain the gate. "It's critical to measure the depth and undercut beneath the gate to determine stress," McMillan said. "It goes beyond CDs; we call it 'shape measurement.'" Logic manufacturers must also know the width at the gate's bottom to control implant, which can be notched to be smaller than that seen from the top down. The pull-down of the spacer from the top of the gate is also important, as this influences how much salicide grows on the top of the gate and reveals a lot about gate resistance.

Device makers want to measure the full shape, and those doing logic require high precision — if the gate is controlled, so is device speed. Memory is more demanding about shape because manufacturers want the equivalent of a cross-section TEM that works non-destructively inline at high throughput. "We're measuring in flash things like the floating gate structure, which includes several different oxide depths besides the CD," McMillan said. "DRAM makers want to measure recessed gates, where the gate doesn't sit on the silicon, but on a trench etched into it. That recess gate determines gate length and speed, so they must know the CD and the depth under the gate." With 45 nm DRAMs, some are considering finFET structures, which are 3-D transistors. CD-SEMs cannot effectively measure this, as it requires optical technology.

The CD-SEM's role is changing. With advanced patterning techniques, measurements must be done to control things like hot spots. Advanced optical proximity correction (OPC) is used, and the CD-SEM checks specific locations within the device to ensure that they are properly printed. It is more like a top-down inspection check at certain locations based on models of where layout failures may occur.

Doubtless, 32 nm will be challenging. One hurdle arises from the patterning techniques being adopted; for flash, phase-pitch splitting is coming. It uses standard lithography, but film and etch techniques are applied to double the pitch, resulting in twice as many lines in the same area. The deposited film's thickness, spacer shape and final lines' CD must be measured. After the spacer deposition and etch, manufacturers measure the spacer's width and shape to ensure that, after the stack etch, the final pattern is obtained.

Logic is moving toward high-k/metal gates and strain. This is challenging for film, but there are already tools that can perform it. For optical critical dimension (OCD), it is a challenge because the film stack is more complex (with thin low-k materials introduced) and precision and matching requirements are tighter. Other challenges are double patterning (DP), which is difficult for overlay and CD. Tools that can measure CD and overlay are currently under development. However, the precision required for overlay is staggering: At 32 nm half-pitch design rules, the budget is cut in two. Using DP lithography, a CD or an overlay error almost becomes the same thing because two interacting lithography layers are being processed together.

Modeling solutions are also under development for DRAM finFETs, but logic finFETs will be more difficult. The fins are expected to be <10 nm wide — miniscule, densely packed 3-D structures, usually on a silicon on insulator (SOI) wafer, with exotic films such as the gate dielectric, which are all high-k and difficult to measure. "Generally, we use a 150 SE to be able to get sensitivity on those films, and there is also a need to measure composition as well," McMillan said. "Again, this is a matter of measuring shape because the fin's interaction volume and the gate on top is crucial, and the CD alone doesn't show the interaction volume. You must know how high and wide the fin is, the film property over it, and its profile."

There is a trend toward measuring more device-like structures. The scribe is etched to different depths and not patterned like the die. Some manufacturers want to measure fully patterned scribe areas, which requires a scatterometry technology that can measure films on structures and structures on structures. Memory makers generally want to measure the array area in the die. Usually, that is a 3-D structure; it means measuring not only the CD, but also the full shape. These types of measurements are challenging, both on modeling flexibility and hardware sensitivity.

Rudy Kellner, director of data storage and MEMS marketing at FEI Co. (Hillsboro, Ore.), sees a need to go beyond conventional CD-SEM into S/TEM or TEM. "Besides looking at new SEM technologies that promise significant gains in resolution, we're also investing in automated S/TEM and TEM capability — either analytical capability or actual metrology," he said.

2. A S/TEM lamella created with an automated dual-beam process platform is shown here. With the use of more complex techniques, the complexity and cost of making samples measurable or imageable rise, putting a premium on simplifying the process. (Source: FEI Co.)

CD-SEM is still the fab's workhorse, according to Ram Peltinov, product manager for SEM metrology at Applied Materials (Santa Clara, Calif.), and seems to be the preferred technology of choice beyond 32 nm because it already provides creditable measurement down to 2X and 1X structures. It has also proven to be stable in the long-term in a production environment. Besides, according to Peltinov, 32 nm trends favor CD-SEM vs. optical alternatives. "Among these trends are 2-D dense shapes resulting from changes in design density of DRAM structures going from 8F² to 6F² and to 4.5F²; the increase in the number of materials, and the amount of pitch-splitting techniques, such as line by spacer, line by fill, and litho-etch-litho-etch double patterning," he said.

The complexity of optical recipes creation is significantly increased by 2-D shapes with non-trivial repeating schemes combined with the many new materials. In contrast, CD-SEM is on the opposite path for easing recipe creation activity through CAD-based automatic waferless recipe creation, simplifying the creation of high-quality recipes at a zero time-to-market hit.

Pitch-splitting techniques being developed by Applied Materials process groups create dense lines and spaces that originate from two different steps. "Distinguishing core space from gap space is critical, and you cannot just average the whole array as optical techniques do, assuming that all spaces and lines are equal," Peltinov said. The CD-SEM can provide detailed information on core space, gap space and spacer-width CD, including the line-edge roughness (LER) and linewidth roughness (LWR) characteristics of the spacer that become significant at 3X-1X CDs.

For litho-etch-litho-etch double patterning (LELE DP), where the overlay measurement is the largest challenge, CD-SEM is best because both layers are visible and the tool provides better resolution and precision.

Noam Shintel, corporate marketing manager at Nova Measuring Instruments Ltd. (Rehovot, Israel), thinks that optical metrology will provide the necessary critical shape profile parameters, such as sidewall angles and multiple spacers' widths. "Optical metrology will be the technology of choice for CD measurements," he said. "However, together with the benefits of full-shape profiling, high throughput and low COO, comes the complexity of developing optical CD applications, where there's a need to accurately model the structure and determine the underlying layers' optical properties."

Optical metrology is challenged by reduced development cycle times requiring push-button automation. As the business models for semiconductor manufacturers change, average selling prices (ASPs) fall rapidly and time-to-market becomes increasingly critical. Only tools providing high automation levels will cope with the added complexity of CD applications at 32 nm and below.

A second challenge results from technology barriers pushing lithography into DP with no apparent alternative (like extreme ultraviolet [EUV]) until possibly the 22 nm node. "Double patterning overlay errors result in CD errors and vice versa," Shintel said. "Several double patterning schemes are being proposed. The industry hasn't decided which is best," he said. DP poses a major hurdle — not only must metrology provide unprecedented precision, but it must also provide high throughput comparable with scanner throughput and the large sampling required to control DP. This is made more difficult because the correlation between CD and overlay dictates that both be measured on the same site, while today they are measured using different tools, sites and technologies.

Applied's CTO for etch, Uday Mitra, explained that CD measurement is critical for self-aligned DP (SADP) or spacer patterning being used for <40 nm half-pitch for NAND and NOR flash, but that current metrology tools and the International Technology Roadmap for Semiconductors (ITRS) have this requirement covered. Because of high conformality and good reproducibility of spacer films and prior use as device spacers, metrology for spacers is not really necessary. LER and LWR become major issues at smaller dimensions, and while they do not present much of a metrology issue, it is challenging for processing; SADP approaches with advanced patterning film give much better LER and LWR.

For DP using a LELE technique, improved metrology for overlay is needed. Also, LELE runs into 2× the LER issues compared with SADP, and LER and LWR can confuse metrology matching. Two CD-SEMS may give different CD results because of LWR and LER variations in a sample rather than true matching, unless it is measured at exactly the same spot. LER 3S values can be as much as 5× the metrology spec values.

Increasing aspect ratios of contact and DRAM capacitor structures present another challenge. Today, there are no good non-destructive methods of measuring high-aspect-ratio contacts. Aspect ratios could go as high as 40:1 in future nodes. Here, inline metrology is lacking and further development is needed.

John Samuels, director of product marketing at ReVera (Sunnyvale, Calif.), sees the awareness and impact of coupled and decoupled measurement results on complex metrology applications becoming critical. "Before, single two-component films with very stable material and very stable optical properties, such as SiO₂, Si₃N₄ or even TiN, were easily measured by optical metrology. CDs were well within CD-SEM resolution with simple profiles," he said. Now, traditional methods are insufficient in the process parameter space in critical applications; for example, gate SiO₂ has progressed to HfSiON or LaHfSiO and CD profiles with undercuts and 3-D structures (Fig. 3).

3. As variables are added, coupled techniques exhibit increasing relative uncertainty. In a real-world 3-D example, thickness, nitrogen and hafnium percentages in HfSiON, both methods have the same intrinsic measurement variability but different coupling degrees represented by ellipsoids. As with SiON, the optical measurement shows less uncertainty along the X axis and greater uncertainty along the Z axis (% N) with a moderate degree of parameter coupling (left), thus an effective measure of thickness. Optical techniques show greater uncertainty in the composition measurement (right) with a high degree of coupling between %N and %Hf. The XPS signal for composition is very symmetrical, indicating minimal coupling between parameters. (Source: ReVera)

Indirect metrology systems measure signals unrelated to the parameter of interest. These signals are then correlated to desired material and process control parameters, such as thickness, composition or CD. This is done for expedience because indirect measurements are typically fast and do not require complex hardware. Examples would be optical thickness or CD measurement, coronal discharge or four-point probes.

Indirect metrology's problem is that the signals measured are typically influenced by multiple physical parameters. Changes in one parameter, such as thickness, may give the same signal response as a chemical composition change. Thus, these parameters are "coupled" in the measurement. In such a coupled measurement, one cannot unambiguously determine the change in physical parameters from the metrology response — just that something has changed. A second critical ramification is that the intrinsic sensitivity to changes in the parameter of interest is influenced by the coupled parameter's sensitivity and variation, possibly affecting fundamental accuracy and precision. The more parameters that are coupled together, the worse the problem.

In a direct measurement system, the signals measured are usually unique to the parameters one is trying to control. Thus, other parameters' variations in the system have little or no impact on the signal of interest; they are "decoupled," allowing for definitive process control. "The addition of more decoupled measurement parameters doesn't affect the intrinsic target parameter's measurement accuracy," Samuels said. These direct techniques usually use signals that probe the parameter of interest at a fundamental level, such as individual atomic transitions or physical structure size, and require more complex technology, resulting in higher cost and lower measurement speed (i.e., electroplated metals abatement system [EPMA], X-ray photoelectron spectroscopy [XPS] or atomic force microscopy [AFM]).

Paul Ter Beek, senior product manager for opaque and transparent thin-film products at Rudolph Technologies (Flanders, N.J.), thinks that the key to meeting measurement requirements is implementing a metrology method that allows high sample rates and non-destructive measurements of the basic core — the transistor's workfunction. "All we've done in past decades is measure derived parameters to support that workfunction's control," he said. Most common parameters for process control systems are thickness, composition, CD and stress. Advanced devices also require spatially resolved parameters, such as shape and compositional gradient. In even relatively simple OCD cases, there are issues with sidewall angles that cannot currently be measured accurately. This is a signal-to-noise ratio problem, pertaining to the limited response received from variations in sidewall angle, making signal-to-noise performance critically important.

Metrology faces many issues at the 22 and 18 nm nodes. For instance, dimensional shrink and quantum effects will increase copper resistance, raising the possibility that it may not be useful at 18 nm, requiring again a different material. If one considers devices at the 130 nm node, except for the poly and SiO₂, all the materials have changed. If metal gates, copper and other materials are used, the interlevel dielectric (ILD) changes. There is almost no commonality of materials between current advanced devices and just a few generations' older ones.

This looming avalanche of new materials and an increase in complexity of device designs will not only require better repeatability and matching but, unfortunately, will also increase the number of noise sources. The only answer is better tool designs and an increase of data. Data increase can be achieved by increasing measurement dimensions. Wavelength ranges have already been increased, time-resolved measurements will be needed, and higher angles of incidence need to be measured. We definitely are not at the end of optical metrology — the wavelength range has been pushed to 120 nm; however, that is only one dimension.

Additional dimensions must be added, and data should be obtained from where the sensitivity is located. Thus, extending along one dimension to bring data from a wider or broader wavelength is not always useful. If one deals with materials that exhibit sensitivities at specific wavelengths, more or better quality data may be collected by expanding polarization measurements and measuring time-resolved responses. This exploits the benefits of non-destructive optical metrology: speed and cost.

Considerable developmental work is taking place on copper deposition, through-silicon vias (TSVs) and 3-D interconnect-type applications. Tom Ritzdorf, director of ECD technology at Semitool Inc. (Kalispell, Mont.), said, "Some of these seem similar. A cross-section looks similar to submicron damascene, vias; however, feature sizes are orders of magnitude larger, which means a different process mechanism."

According to Ritzdorf, other areas experiencing considerable activity in copper deposition are plated copper lines for distribution layers. "Those typically aren't damascene architecture, but additive plating through photoresist masks, where copper thicknesses may be in the 5–10 μm range," he said, adding that there is also significant activity with copper pillars that may have tin or tin/silver caps for bonding applications. TSV challenges have been in defining the process window and controlling the process, increasing deposition rates and improving throughputs. There is considerable work going on with processes around the plating process (etch, barrier seed, CMP, bonding, wafer thinning).

"For years, people have talked regarding damascene processes about things like seed layer enhancement and direct-on-barrier copper deposition," Ritzdorf said. "Some of those more novel processes might be more easily adopted in TSV applications. We have our own seed layer enhancement process, which has been implemented in production. The direct-on-barrier copper deposition processes are gaining traction and results look good."

Ritzdorf believes that a fundamental understanding of how mechanisms differ for TSV vs. submicron damascene interconnects is needed. This would allow for a more efficient optimization of the processes and increase the process window size, quickening the implementation of 3-D processes. However, as with so many factors in semiconductor processing, metrology will be essential for this achievement.