Flip-Chip Changes on the Horizon
Flip-chips haven’t changed much since being invented by IBM in the early ’60s, but some interesting trends are emerging and several potential changes are on the horizon.
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 7/2/2008 9:00:00 AM
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But some very interesting trends are emerging in the flip-chip arena, with several potential changes on the horizon.
To start with, demand for flip-chips is on the rise thanks, in part, to a spike in gold-bonding wire costs. “Significant trends are taking place because the cost of gold wire is increasing,” explained Raj Pendse, STATS ChipPAC’s (Singapore) vice president of flip-chip and emerging products. “Mobile products or platforms that traditionally used wire bonding, 3-D and stacked die are now an area in which we see future growth potential. A couple of performance reasons are also helping drive a shift to flip-chips: You can miniaturize better with flip-chip, and the silicon used in mobile applications is becoming more dense [higher I/O density]. Rising gold prices have pushed that crossover point to a lower pin count, though. Mobile and handheld applications are typically in the 200-700 pin count range. The crossover point for flip-chip used to be around 1000 I/O, where most of the computing and game consoles are. But now it’s come down to about 500 I/O. From a broad performance and cost perspective, I’m seeing a very big shift into the 200-700 pin count applications — starting with mobile products for cell phones, digital cameras and other handheld products. The way the industry is responding to rising gold costs is to move to copper wire or finer-diameter wire bonding. Or considering making a move from wire bonding to flip-chip instead.”
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| Demand for flip-chips, such as this flip-chip ball grid array (BGA) system-in-a-package (SiP), is on the rise. (Source: STATS ChipPAC) |
FlipChip International (Phoenix) is also seeing a shift from wire bonding to flip-chips. “There definitely seems to be a continued trend of migration toward flip-chip, driven by the cost of gold wire,” noted Ted Tessier, FlipChip’s CTO. “I don’t think we’re seeing the complete effect of this happening yet, because there’s a lot of work required to transition from products that are primarily wire bonded over to flip-chip. But it appears to be underway.”
And Pendse pointed out that design methodology for chips is very different when comparing wire bonding and flip-chip. “With the new silicon generations, starting at 45 nm, many of our customers are deciding that it might not be worthwhile to sustain two kinds of design methodologies for the same application. If there is a small cost difference one way or another in the total cost of the package, they are choosing to design new silicon directly into area-array layouts for flip-chip interconnection. While it won’t have a big impact on 2008 or 2009 revenue, it should have an impact on 2010 revenue. To some extent, this is being accelerated by the gold wire cost issue,” he said.
Yet another trend emerging is related to the growth in embedded die technologies. “We’re doing some work to support embedded die technologies,” Tessier said. “At this point, we’re customizing die for embedding and it seems like the highest-volume application coming along within the next year or two will be related to embedding devices, possibly passive devices like silicon, into cell phone boards and laminate substrates.”
Changes on the horizon for flip-chips? The European Union’s RoHS lead-free regulations and new halogen-free requirements are bringing significant technology-related changes. “The bump in flip-chips will be required to be lead-free in the near future,” Pendse said. “There were RoHS exemptions for flip-chips, so the bump didn’t need to be lead-free. Under that exemption, which will expire in 2010, many companies didn’t change the bump to lead-free. Companies that made the transition are using copper instead. As the bump goes lead-free, the bill of materials is also going halogen-free, which includes substrates that are not halogen-free today. The lead-free change is creating many problems. For example, the cost of bumping is different and the reliability of the package isn’t on par with the old structure. Materials for underfill need to be different to match with lead-free bump properties, so numerous new issues are cropping up. It’s spawning development in underfill materials, substrates, etc. And determining which lead-free composition is the best one has been a big challenge.”
Another challenge is how to make a cost-effective substrate for a flip-chip package. There’s a drive to migrate to flip-chips for many reasons, but also because of the need to streamline the design. Flip-chip substrates today cost roughly 2× as much as wire-bond substrates. To make a lower-cost substrate, the industry is looking at new ways to efficiently route and design interconnection of the chip to the substrate. “You cannot route any signals on the top layer of the substrate, so it requires multiple layers,” Pendse said. “So we’re now looking at ways to make that fine I/O interconnection to get enough routing space on the top layer of the substrate and keep the layer count at 2-4 layer with laminate in design rules. The substrate will become closer to a wire-bond substrate. This is going to be a major change within the next two years.”
And of course, how do flip-chips fit into 3-D integration? “We’ve come up with a way to combine flip-chip and wire bonding in stacked integration that we call a hybrid flip-chip package,” Pendse explained. “Since you cannot just put four flip-chips on top of each other because there’s no mechanism to do that today, we’ve combined wire bonding and flip-chips to convert the most I/O dense area to a flip-chip and put it into the bottom and put wire-bond die on top of it. It comes with its own bag of issues, however. How do you create a surface finish? One on which you can wire bond and do flip-chip as well. How do we combine underfill and wire bonding? This is a new realm of packaging. We’re doing a lot of work in this area right now. The move to 3-D packaging with through-silicon vias is actually a good fit for flip-chips because when you make TSVs, you can put one flip-chip on the back of another flip-chip.”
It’s been years in the making, but flip-chips are finally being widely adopted in the industry. “Wafer-level chip-scale packaging {WLCSP] has been strong the past several years and is continuing to grow,” Tessier said. “Flip-chips are also starting to be used more in high-volume SiP for wireless applications. And we’re seeing newer bumping technologies like the copper pillar bump really take off.”
As far as how the flip-chip market is performing, Jim Walker, vice president of research, semiconductor manufacturing, Gartner (Stamford, Conn.), said that continued drive to integration via increased density and improved performance is playing into the demand for flip-chip-based packages.
“Many of the substrate suppliers for IC packages and flip-chip interconnects are optimistic about the second half of 2008,” Walker elaborated. “The PC market demand now looks stronger than expected earlier in the year, so chipset and graphics card markets that use flip-chips should improve in the second half. Orders for flip-chip substrates used in game consoles and continued growth in digital TV will further increase the adoption of flip-chip in the second half as well. Orders for high-end cell phones and PDAs using flip-chip CSP are stronger than other applications. And the use of flip-chip substrates based upon bizmaleimide-triazine used in FPGA devices increased in Q2, and will continue to grow in the second half. All of this increased growth bodes well for the flip-chip market. The industry hasn’t seen much increase in package substrate capacity in the past two years, which will result in a tighter supply with more stable prices.”
