IMEC Devises Simplified High-k/Metal Gate for 32 nm

Staff -- Semiconductor International, 6/17/2008 8:32:00 AM

At today’s VLSI Symposium on Technology in Hawaii, IMEC (Leuven, Belgium) reported improved performance for a planar CMOS device using hafnium-based high-k dielectrics and tantalum-based metal gates for the 32 nm CMOS node. The inverter delay was reduced from 15 to 10 psec (Figs. 1 and 2). IMEC simplified its high-k/metal gate process by decreasing the number of process steps from 15 to 9. This process demonstrates the compatibility of conventional stress memorization techniques with high-k/metal gate for the first time, according to IMEC.

1. SEM and cross-sectional TEM (inset) of NMOS/PMOS boundary in ring oscillator.

High-performance (low threshold voltage [V_t]) high-k/metal gate CMOS has recently been achieved by applying a thin dielectric cap between the gate dielectric and metal gate. Both gate-first and gate-last integration schemes have proven to be successful. While the gate-last scheme has now been introduced into production for high-performance products, the gate-first option remains attractive for low-cost applications if its complexity can be reduced to the standard CMOS process flow. One of the possibilities for gate-first is a dual-metal, dual-dielectric process flow using mostly hard masks to pattern NMOS and PMOS regions selectively.

By applying conventional stress boosters to its gate-first, dual-metal, dual-dielectric high-k/metal gate CMOS, IMEC increased the performance of NMOS and PMOS transistors by 16% and 11%, respectively. This results in an inverter delay improvement of 5 psec, decreasing from 15 psec to 10 psec.

The researchers simplified the process complexity from dual-metal dual-dielectric to single-metal dual-dielectric by using soft mask processes and wet removal chemistry. The process reduces the complexity by 40%, or six steps, compared with dual-metal dual-dielectric. It also allows simpler gate etch profile control and better prospects for scaling.

IMEC also proved that the use of lanthanum and dysprosium capping layers do not show any reliability issues.

These results were obtained in collaboration with IMEC’s sub-32 nm CMOS partners, including Intel, Micron, Panasonic, Qimonda, Samsung, TSMC, NXP, Elpida, Hynix, Powerchip, Infineon, Texas Instruments and STMicroelectronics.

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