IBM Takes Gloves Off for 32 nm Low-Power Competition With TSMC
IBM engineers described the Fishkill alliance’s low-power 32 nm process technology, which includes a high-k/metal gate stack, at the 2008 Symposium on VLSI Technology. IBM Vice President Gary Patton said the insertion of high-k will give the partners several advantages over foundry rival TSMC, which plans to stick with an oxide/poly gate stack. “Poly oxynitrides are going to be quite a bit more expensive than using high-k/metal gate at 32 nm,” Patton said.
David Lammers, News Editor -- Semiconductor International, 6/26/2008 10:48:00 AM
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| IBM and its alliance partners described a 32 nm technology for low-power applications at the 2008 Symposium on VLSI Technology. |
TSMC unveiled its 32 nm low-power transistor at the 2008 International Electron Devices Meeting (IEDM) last December, and discussed its 32 nm rollout plans again in April at the TSMC technology symposia in several U.S. cities. For low-power and general-purpose applications, TSMC plans to stick with a conventional gate stack to keep costs down, but will adopt aggressive embedded silicon germanium (eSiGe) strain techniques, according to its IEDM presentation. TSMC plans to introduce a high-k dielectric for the high-performance 32 nm process it is developing for the Sun microprocessors.
Patton said TSMC has it all backwards, arguing that “poly oxynitrides are going to be quite a bit more expensive than high-k/metal gate at 32 nm.” Companies that use poly oxynitrides at 32 nm will have to go to a triple oxide process, he said, adding that “to get anywhere near decent performance, they will have to go to a thin oxide, which increases leakage.” Embedded SiGe strain engineering will raise costs, he argued.
Mukesh Khare, project manager for high-k/metal gate technology at IBM, said, “We are introducing one big element: high-k. For a company that sticks with an oxide poly approach, they have to throw in the kitchen sink, putting in stress liners and other stuff. It is more cost-effective to do one big element than a bunch of smaller elements to get to the same performance target. With our approach, we do not need to add SiGe strain engineering for the PMOS for low power. TSMC will be throwing in all kinds of strain engineering, which is contrary to what you are trying to achieve for a low-cost mobile product, where you want a very low-cost process.”
The IBM engineers said that because high-k adds such advantages at 32 nm, many customers will skip the 45/40 nm generation and go directly to a 32 nm process. Patton added that the 32 nm ground rules were developed with an eye on an easy transition to a 28 nm half-node offering. “Some customers may bypass the 45 nm generation in order to take advantage of high-k,” Patton said.
Khare said, “Our integration approach allows us ground rule compatibility from 45 or 40 to 32 nm and migrating forward to 28 nm. We did not introduce any additional ground rules when we introduced our new element: high-k/metal gate. That is very different from other methods of high-k/metal gate, where you have to be very careful of ground rules and introduce more polishing.”
With the Fishkill partners competing with TSMC for share of mind at the lucrative 32 nm mobile market, IBM engineers have become aggressive in claiming power advantages. In December 2007, IBM reported that it had created a test 32 nm SRAM. Last April, it said it was ready for customers to begin 32 nm designs.
An Steegen, the 32 nm bulk CMOS project manager at IBM, said high-k/metal gate allows IBM to reduce the low-power oxide thickness by ~10 A to a 14 A inversion thickness (Tinv). The thinner gate oxide improves performance, allows the gate length to be reduced to 30 nm, and keeps the SRAM Vmin to the optimum level. Contacts can be placed closer together without danger of shorting effects.
At the 32 nm generation with an oxynitrides technology, short-channel effects become onerous, she said. “High-k is key to controlling a short channel, which is a big problem when still using oxynitrides. We can be aggressive with L scaling and L poly scaling and still get much better short-channel control than with an oxynitrid technology,” Steegen said.
IBM is offering a multi-project wafer shuttle program, with the run scheduled for September sold out in May. A second shuttle is planned for December. IBM and its Fishkill partners plan to begin manufacturing the 32 nm low-power process in the second half of 2009. Patton said, “Our 32 nm process makes it easy for customers to migrate their IP from previous generations. For one thing, transistor drive current ratios are very similar to what they are at 45. If a design is port to a 32 nm process with a nitrided poly gate stack, the drive current ratios drop significantly and that would require some significant redesign work.”
Khare said that with eSiGe employed, the designers must deal with pitch- and layout-dependent effects, which change as the device geometries shrink. “Strain adds new challenges from a design perspective,” he said.
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| Gate leakage is plotted against the inversion thickness for oxide/poly and high-k gate stacks. |
Acknowledging concerns that a high-k/metal gate process introduces high costs, Chen said, “Less than 3% total process cost is added with high-k/metal gate compared with a poly-SiON gate stack. The use of a hafnium-based high-k gate dielectric allows us to maintain a low gate leakage of <0.1 A/cm2 while continuing to provide substantial room for EOT scaling.”
The SRAM cell size is 0.157 µm2. NMOS/PMOS drive currents were 1000/575 µA/µm at 1 nA/µm off-current and a 1.1 Vdd, which can be scaled to 1.0 V for active power reduction.
Steegen said customers will continue to use multiple power rails and other design techniques to control standby power. The insertion of high-k/metal gate means active power will be improved, allowing 32 nm customers to employ dynamic voltage scaling to manage active power.
“The big issue at 32 nm is active power management and control. High-k gives us enough margin on performance that we can book that by Vdd scaling. We can meet certain performance requirements at 0.9 V and get active power savings,” she said.
