Intel Scales Floating Body Cell Memory

David Lammers, News Editor -- Semiconductor International, 6/19/2008 9:51:00 AM

At the 2008 Symposium on VLSI Technology in Honolulu yesterday, Intel Corp. (Santa Clara, Calif.) researchers presented work on a floating body cell (FBC) memory that uses a thin layer of buried oxide (BOX) to store the charge, based on a silicon on insulator (SOI) technology. The research indicates that the FBC technology could potentially be introduced at the 16 nm node and further scaled to the 10 nm technology generation, a significant endorsement for a memory type that some experts have said would face charge-retention challenges as scaling proceeds.

Intel developed a floating body cell (FBC) device using a 10 nm buried oxide (BOX) layer, with a 32 nm gate length.

While other FBC studies have used a thick buried oxide, the Intel team created a thin 10 nm BOX layer, with a 22 nm silicon thickness, said Mike Mayberry, director of components research at Intel. While it is “not quite as fast” as conventional SRAMs, Mayberry said that the FBC memory would enjoy a much smaller cell size than the six-transistor (6T) SRAM now used, adding that 6T SRAM technology “can continue to scale, but has some optimization problems.”

“A single transistor memory would be so much better [than a 6T memory] if we can make it work,” Mayberry said.

Mayberry said the FBC memory obviates the need for a separate capacitor, which is expensive to build. By putting the capacitor in the body of the cell, he said the FBC approach can put in 3-4× more bits per area. More bits within a given area could translate to faster computations, and the FBC approach is potentially less costly. Also, Mayberry said the thin BOX and silicon layers will support lower voltage operation compared with thick SOI cells. With a 30 nm gate length (L_g), the Intel FBC would yield a cell size of ~ .01 µm².

The research team adapted Intel’s 45 nm logic technology for the experiment, with front and back gates implemented in a planar architecture with raised source/drain regions and undoped wells. Titled, “A Scaled Floating Body Cell Memory with High-k + Metal Gate on Thin-Silicon and Thin-BOX for 15 nm Node and Beyond,” the authors are from Intel’s Technology Manufacturing Group (TMG) in Hillsboro, Ore., and include Ibrahim Ban, Uygar Avci, David Kencke and Peter Chang.

The researchers presented data from fabricated devices with 60 nm L_g devices, demonstrating small threshold voltage (V_t) variations as well as good device and memory characteristics. Besides the 60 nm devices, the authors wrote that “functional 32 nm gate length silicon suggests the feasibility of this technology at the 11 nm node,” adding that the 32 nm L_g devices are the smallest reported to date. “Undisturbed retention was measured at >100 ms in a wide, short 32 nm L_g device and demonstrates the possibility of scaling the technology,” they said in the paper.

At the 16 nm technology generation, the FBC would have a much smaller cell size than a 6T SRAM. With a 40 nm L_g, a 60 nm space between the gates, and a 60 nm metal pitch, the FBC cell size would be 0.012 µm² for a folded bit-line design and 0.006 μm² for an open bit-line architecture.

The Intel study injects new optimism into the technological debate over FBC memories. IBM researchers, for example, have studied the approach and concluded that it would be difficult to retain the charge in the BOX as scaling proceeds.

Late last year, Innovative Silicon Inc. (ISI, Lausanne, Switzerland) announced its second-generation Z-RAM design. ISI, one of the pioneers in the FBC field, has signed licensing contracts with Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.), Hynix Semiconductor Inc. (Icheon, Korea) and others. In Japan, both Toshiba Corp. (Tokyo) and Renesas Technology Corp. (Tokyo) have actively pursued FBC research.

“The FBC cell could result in a cache that is a factor of 30 smaller than the 45 nm cache,” built with 6T SRAM technology, Mayberry said, adding that the technology would be viable for productization at the 16 nm generation or beyond. The Intel FBC research devices are two generations smaller compared with other published work, he said.

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