Date: July 15, 2008

Location: The AMD Commons Bldg, Sunnyvale, Calif.

This advanced tutorial will cover the impact of silicon technology scaling on ESD device behavior and on subsequent ESD protection design. The physics of CMOS components under high-current conditions will be discussed. Also, the technology trends for sub-100 nm nodes and their implications for the ESD design window will be covered. Finally, sub-50 nm technology challenges will be discussed. This class is intended for individuals who have taken the basic on-chip protection class and are familiar with basic device physics for both ESD and latch-up.

www.esda.org/education.html