When Will 450 mm Make Economic Sense?
There is an industry-wide curiosity about the reality behind a wafer size transition to 450 mm. According to the International Technology Roadmap for Semiconductors (ITRS), this transition should happen in 2012 to keep the industry on Moore’s Law, and a few companies are pushing hard to make this happen.
Jonathan Davis, Executive Vice President, Global Expositions, Marketing, Communications and EHS, SEMI, San Jose -- Semiconductor International, 7/15/2008 7:22:00 PM
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There is an industry-wide curiosity about the reality behind a wafer size transition to 450 mm. According to the International Technology Roadmap for Semiconductors (ITRS), this transition should happen in 2012 to keep the industry on Moore’s Law, and a few companies are pushing hard to make this happen.
However, the fundamental assumptions that are driving the push for this transition are overstated. Moreover, limited R&D dollars available to tool and equipment suppliers means that investing R&D capital prudently is essential to the survival of many companies in the supply chain. A white paper released by SEMI in 2005 showed that industry R&D dollars are becoming more constrained as advanced process R&D costs rise.
A transition to 450 mm wafers is an extremely expensive and risky proposition — estimates run to well over $25B at the high end. The industry simply cannot afford to make such an expensive investment based on future "expectations" without an objective analysis of cost and benefit.
To determine the best path forward for the industry, the Equipment Productivity Working Group (EPWG) was formed 2.5 years ago as SEMI and the International Sematech Manufacturing Initiative (ISMI) worked to analyze the economic realities of the future of the semiconductor industry. The EPWG has finished its economic analysis, and results clearly show that the right time for 450 is not now and, perhaps, not ever.
But the myths about 450 mm, and indeed any wafer size change, still persist. "The 450 mm Transition: When Will It Make Economic Sense for the Semiconductor Industry Ecosystem?" session, held Thursday, will start off with a presentation by John Ellis, vice president of Global Standards and Technology at SEMI, who will report on the findings of the EPWG. The focus of this presentation will be a discussion of the five major misconceptions about a transition to 450 mm wafers, and will show, in detail, the underlying assumptions and flaws of the conclusion. After the presentation, a panel of equipment and materials company executives will discuss the results of the study, offer their perspectives on the conclusions, and then proceed to a Q&A session to allow interested attendees a chance to follow-up.
Ellis’s presentation will begin with the observation that technology advancements are the largest lever we have to continue along Moore’s Law. The semiconductor industry’s history is one of relentless innovation in many areas, but changes in product use and consumption are forcing executives to make difficult decisions about investment choices for the future.
The industry is now in a consumer-driven market, which means fabs and foundries need to run small lots and be extremely agile in their product mixes. Cycle time is paramount, as lengthy time-to-volume and time-to-market can exclude companies from profit opportunities. And notably, there is an R&D funding gap.
A commonly held industry expectation is that a wafer size change provides significant benefits. The EPWG took a long and careful look at the costs and benefits of a wafer size transition, and along the way, several wafer-size transitions misconceptions were examined. These "myths" will be discussed in detail during the presentation and panel.
"A 50% wafer size changes occur every 10 years" — The length of time between equivalent 50% wafer size increases has steadily grown in time over the past four decades as the industry has slowed its growth rate, and is now much longer than 10 years. However, even if this myth were true, a cost-benefit analysis should always be performed to determine if the next change truly makes sense.
"Larger die sizes drive us to 450 mm wafers" — While die size has been a driver of wafer size change in the past, industry analysis from Wright Williams & Kelly shows that current die size is stable or decreasing.
"Wafer processing costs drive overall chip cost reduction" — An examination of the cost structure of current devices shows that a 450 mm wafer increase will impact <10% of final product cost in a positive way. Moreover, there are serious technical and economic issues for the assembly, packaging and test community that are as-yet unaddressed.
"There is a significant productivity gain provided by increasing wafer size" — The EPWG found, through its cost-model analysis, that previous wafer size transitions, in and of themselves, offered little gain. While for some tools there is gain to be found from increased wafer area, many tools, constrained by how much area they can process per hour, show little benefit. Gains from the 300 mm wafer size transition were, in fact, caused by several factors that were independent of wafer size. Many of these improvements, such as the use of FOUPs and automated material handling systems (AMHS), among others, now exist and will not help to incrementally increase performance over 300 mm.
"A wafer size disruption is the only way to force industry-wide change" — A realistic assessment shows that a wafer size change is the riskiest way to force change, because it will exacerbate the R&D funding gap, reduce or eliminate technology advancement on 300 mm, increase cycle time (over 50% more), and steer the industry away from the consumer-driven market trends.
Also to be discussed are programs in 300 mm Next-Generation Fab (NGF), providing a coordinated way to inject improvements into the semiconductor manufacturing process. SEMI is pursing these through collaborative activities with chipmakers within the Equipment Supplier Group (ESG) and EPWG.
