Soitec Ready With Ultrathin SOI Wafers
In a materials advance that could enable multi-gate logic devices and floating body single transistor memories, Soitec said it has qualified a line of SOI wafers that feature ultrathin top silicon and buried oxide (BOX) layers.
David Lammers, News Editor -- Semiconductor International, 7/16/2008 8:00:00 AM
 |
 |
| Soitec's XUT+ wafers. |
The ultrathin SOI layers may permit technologists to create planar structures with a back gate underneath the channel, providing many of the advantages of finFETs while preserving the easier-to-manufacture planar structure, he said.
Also, the thin BOX is required for the SOI-based floating body cell (FBC) memories being developed by Toshiba Corp. (Tokyo), Intel Corp. (Santa Clara, Calif.) and others. At the recent 2008 Symposium on VLSI Technology in Honolulu, Intel researchers presented research on a FBC memory for embedded cache on microprocessors.
The Intel researchers used a thin BOX to store the charge, rather than building a capacitor. The FBC approach would provide a single-transistor memory that would have a smaller cell size, supporting larger cache sizes.
Auberton-Hervé said PD devices do not require ultrathin SOI wafers, but FD devices do. Today’s SOI wafers have a BOX that is 100-140 nm in thickness. The UTX+ wafer BOX can be as thin as 10 nm, while the top silicon layer is available in thicknesses ranging from 20 to 110 nm. Variability of the thickness is controlled up to ±10 Å, or 1 nm.
The wafers can be configured with a high-resistivity substrate or as a strained silicon approach. Some companies are considering a hybrid approach, using an SOI approach for the SRAM and having a bulk silicon area on the die for the logic portion.
The ultrathin SOI wafers will be priced in the same range as the Soitec wafers with the thicker BOX layer, he said, adding that a typical SOI wafer has a $400 premium above the cost of an epitaxial wafer. The oxidation steps are somewhat shorter with the UTX+ wafers than with the thicker BOX wafers. However, yields must be controlled because of the thinner oxide and silicon layers, he said.
“SOI, if not a necessity, is the best way to scale, especially at the 22 nm node and beyond,” he said.
The announcement comes at a challenging time for the company, said Takashi Ogawa, who tracks the SOI wafer market as an analyst for Gartner Inc. (Stamford, Conn.). Soitec’s revenues declined 13% last year after several years of strong growth, and the company has been campaigning to gain customers in the low-power space, including cell phones. A new SOI wafer facility in Singapore is being ramped up this year to meet high-volume customers in the low-power space.
“The low-power initiative depends a great deal on the wafer cost. Soitec has to get the cost down to the range of an epitaxial wafer if they expect to get high-volume customers in the phone sector,” Ogawa said. Today, an epitaxial 300 mm wafer is priced at ~$200, he said.
