Roadmap Signals Showstoppers
The overall theme of the 2008 update to the International Technology Roadmap for Semiconductors (ITRS) is a slight slowdown of gate-length scaling for high-performance and low-standby power devices, but the low-power device target dates will not change.
Laura Peters, Editor-in-Chief -- Semiconductor International, 7/17/2008 8:00:00 AM
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On the More than Moore panel, talk of 3-D approaches using through-silicon vias (TSVs) was the hot topic. Juan-Antonio Carballo, chair of the design TWG, talked about how More than Moore brings new system drivers as well as design requirements. Roger Barth, test TWG, commented on the challenges of system-in-a-package (SiP) testing, where very high-yield and low-cost test approaches are needed. “We need to guarantee the vias and be able to expand the architecture across multiple die,” he said.
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| (From left) Bill Chen, Juan-Antonio Carballo, Margaret Huang, Roger Barth and Chris Case made up the More than Moore panel during ITRS presentations. |
William Chen, chair of the assembly and packaging TWG, stated that major changes are happening in wafer-level packaging (WLP), SiP, 3-D, embedded components, materials changes and the cooperation around the world. Wafer-level chip-scale packaging (WLCSP) is the fastest growing packaging technology because of its inherent lower cost, improved electrical performance, lower power required and smaller size. Chris Case, chair of the interconnect TWG, commented that for the next 15 years, interconnects will be based on the copper and low-k multi-level structures the industry implements today. With regard to low-k dielectric extension, he said that the k effective of 2.0 is possible using air gaps, but we have yet to determine whether the integration schemes will enable it.
