IBM Alliance Builds 22 nm SRAM Cell
IBM and its semiconductor research partners said they have built a working 22 nm SRAM cell with an area of 0.1 um2. The partners plan to describe the SRAM cell in more detail at IEDM, planned for Dec. 15-17 in San Francisco.
Staff -- Semiconductor International, 8/18/2008 9:42:00 AM
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| IBM's 22 nm SRAM cell has an area of 0.1 µm2. |
IBM said the researchers optimized the SRAM cell design and circuit layout to improve stability. The SRAM cell includes a high-k/metal gate stack, a 25 nm gate length, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.
The researchers built the cell at CNSE, where IBM and its partners perform much of their semiconductor research. IBM spokesman Ron Favali said he could provide few additional details, noting that the brief announcement of the working cell precedes a paper to be presented at the IEEE International Electron Devices Meeting (IEDM), planned for Dec. 15-17 in San Francisco.
The announcement comes less than a year after IBM announced its 32 nm SRAM with high-k/metal gate technology.
