Increasing Demands Require New Look at Wafer Cleans

As device structures scale down, it is getting increasingly difficult to achieve low material loss while still removing particles. It is also getting more difficult to keep from damaging, attacking or otherwise modifying surrounding materials and structures — including doped silicon loss, changes in the k values of low-k dielectrics, metal gate corrosion, pattern collapse, and more. And at 32 nm and beyond, it is all just that much more critical. "I think that's really going to create a paradigm shift in how we do cleans," said Joel Barnett, senior member technical staff, advanced gate cleans, for the Front End Process Division at Sematech (Austin, Texas).

This Raider tool is a high-throughput, single-wafer system for advanced FEOL cleaning applications. (Source: Semitool)

With the way things are going, a more holistic approach to particle removal will be mandatory, according to Mertens, who explained that typical state-of-the-art cleaning methods combine mechanical and chemical cleaning mechanisms that are strongly mutually dependent. But, while chemical aspects are generally studied quantitatively (in terms of etch rates, change in k value, etc.), a more quantitative approach to the mechanical aspects has been lacking. "As a result, the mechanical process windows are not known," he said. "In future cleaning evaluations, one should talk about the mechanical strength of a structure, adhesion strength, etc. — similar to what happens in CMP."

Although resist strip after high-dose implant remains the benchmark for tough cleaning processes, said John Tracy, marketing product line manager for Axcelis Technologies (Beverly, Mass.), ultrashallow junctions are now coming into play as well, making it more difficult to preserve the doped substrate during stripping. "With each new device node, the junction depth or the dopant depth is decreasing," he said. "And that's where the tolerance for any kind of substrate oxidation or substrate damage is coming to a new level of sensitivity."

Use of exotic films in the gate stack structure, such as gate dielectrics like hafnium oxides, is introducing materials that are intrinsically less volatile and harder to remove, noted Jeff Marks, general manager and vice president of the Clean Business Group at Lam Research Corp. (Fremont, Calif.). "So from an etch process point of view, you're generally creating more byproducts," he said. "If you go back to the oldest gate structure of a simple poly structure, etching poly was very clean, and you had almost no residue on the wafer after a poly etch except for the residues that you were intentionally putting down there in order to try and maintain profile and selectivity."

New materials, including tungsten and other metals, leave metal-containing residues on the gate oxide or along the sidewall of the structure, making it difficult to remove the residue without etching away the metal itself in the gate structure. "And at the same time, with the gate structure, instead of a single poly film, now you have possibly four different materials in the gate stack," Marks said, adding that all four of those materials are exposed when doing the clean. "At least when we're doing the etch we're exposing one material at a time as you're etching down, and hopefully you have some sidewall passivation protecting it." During clean, you're trying to remove multiple residues, and expose the underlying material. You don't want to remove any of the underlying materials during the wet process, but you want to remove all of those residues, and that becomes very challenging, he said.

Metal gates have also prompted tool suppliers to explore non-oxidizing ways to strip the photoresist, such as oxygen-free plasma chemistries, according to Tracy. "The oxygen/nitrogen-type plasma chemistries we've used for cleaning in the past are not acceptable anymore with these new materials coming into play," he said. "So, what we've been working on with our customers is a non-oxidizing way to strip the resist and then enable a wet clean."

For more on these and other photoresist stripping issues, see "Resist Removal Walks a Tightrope."

"I really think the post-metal gate deposition will be the most critical clean, and the integration issues associated with that metal gate remain to be the challenge," said Ismail Kashkoush, vice president of applications and technology at Akrion Inc. (Allentown, Pa.). Any metal gate placed in a traditional SC1 or SC2 solution, for example, will just dissolve or get etched away unless protected, he added.

1. A 10 minute HF clean on a single-wafer tool created severe galvanic corrosion of this undoped polysilicon on metal gate. (Source: IMEC)

Metal gate materials continue to be a concern in non-volatile memories, noted Jeff Butterbaugh, chief technologist for FSI International (Chaska, Minn.), and NAND flash will likely have to go to a high-k/metal gate stack as well. Non-volatile memories are evolving from standard floating gate to a TANOS charge trapping configuration, he said, which is driving some material changes. An example of a charge trapping cell stack may include a tunnel oxide, trapping nitride, alumina and metal gate, including a TaN and W/WN layer (Fig. 2). One issue here is that tungsten and tungsten nitride are not compatible with most H₂O₂ mixtures, including SC1, SC2 and SPM, according to Mauro Alessandri of Numonyx BV (Agrate Brianza, Italy), who presented trends for non-volatile memories as part of FSI's Knowledge Services Seminars.

2. Non-volatile memories are evolving from standard floating gate to a TANOS charge trapping configuration. Some new materials, such as tungsten and tungsten nitride, are not compatible with most H2O2 mixtures. (Source: Numonyx)

Although Barnett thinks enough is known to deal with current-generation metal gates, additional challenges will enter the scene as materials advance and people look for ways to remove the new metals. "There will be new challenges as material structure changes," he said. "And that will be continuous."

Alternatives to traditional cleaning strategies for metal gates have included using more dilute chemistries and even water, if possible, along with megasonics, according to Kashkoush. People also have started looking into the use of hydrogenated water, again with the aid of megasonics, as a way to remove contaminants. The technique looks very promising, Kashkoush said, and data is showing that it could replace SC1, for example.

Companies have come up with ideas to electrolytically generate hydrogen from water, Kashkoush explained. The hydrogen acts as an etching agent, helping to weaken the bond between contaminants and the silicon substrate without corroding films. "People have reported that in copper CMP, for example, that's what you need to do," he said. "Because you have exposed copper, you cannot use chemicals that etch copper or corrode copper." Hydrogenated water is also showing promise for cleaning photomasks without attacking the films or etching the chrome, he added.

FSI's Butterbaugh sees a potential for the use of low-oxygen environments for metal gate cleaning. But where he sees an even more pressing need for low-O₂ environments is one of the most demanding areas for cleaning these days, advanced copper/low-k cleaning. Some integration schemes in the copper/low-k area at 32 nm include self-aligned barriers — capping off the polished copper line with cobalt/tungsten phosphide layers. "When you come in and pattern the next layer, etch all the low-k materials and etch your vias down to that metal layer, then you're exposing both copper and cobalt at the same time," Butterbaugh said. "And when you try to clean that, you can set up galvanic corrosion and it can basically etch all of that cobalt layer out of that contact and create a void."

To avoid corrosion, FSI is working on deoxygenated cleaning solutions that involve not only getting oxygen out of the cleaning solution to start with, Butterbaugh explained, but also making sure that the process chamber is purged of oxygen so that it doesn't dissolve back into the solution. "We've had one customer that recently selected our equipment specifically for this application," he said. "These are single-wafer cleaning processes, so they are already very short. And so they saw a need for this even on a short 60-second cleaning process."

At 32 nm and beyond, the dielectric and relative critical dimensions (CDs) can be adversely affected by both wet and dry wafer cleaning processes, noted Dana Scranton, vice president, surface preparation technology and general manager, BEOL/yield enhancement business unit at Semitool Inc. (Kalispell, Mont.). For example, using conventional commercial cleaning media or HF-based media to remove contamination associated with etch and ash steps can result in material loss, which can cause undesirable inductive crosstalk between interconnect copper damascene structures, he said.

New media and process methods are being developed to ensure effective cleans with no significant change in CD, Scranton said, noting that of particular importance is the variation in dielectric constant caused by processing. "In the ideal situation, there would be no change in k value at all," he said. "In reality, however, the k value increases as a result of etch, ash and clean processing. The challenge here is to minimize or eliminate k value shift. This takes the form of new cleaning processes as well as post-etch/ash/clean processing to restore the k value."

Another complication with new materials such as porous low-k and organic films is that they often do not adhere as well as traditional silicon- or polymer-based films and, therefore, can be significant defect sources (see "Bevel Cleans Enhance Yields by Controlling Edge Defect Sources" below). The fluids used in immersion lithography may pick up these and other types of particles from the bevel region and deposit them onto other parts of the wafer, causing growing yield concerns.

To make matters even more complicated, the nature of the interconnect geometries and the materials necessary to achieve sufficiently low k values result in fragile structures, Scranton added, making them susceptible to damage from process conditions that have not previously been of concern. "The porosity essentially can decrease the effective modulus of the structures separating the damascene inlays, which when cleaned can experience collapse due to surface tension or hydrodynamic forces applied through the cleaning media," he said.

Gate structures, in particular, independent of the stack that they're being made out of, are becoming increasingly fragile, and will be increasingly easy to damage, Marks noted. "If you look at one of the biggest challenges in the clean industry, it's this whole aspect of mechanical damage vs. particle removal," he said. "The other structure that's very sensitive to damage is the capacitor structures. And if you look at a 40 nm or a 30 nm memory cell, the capacitor structures almost want to fall over by themselves."

Megasonic cleaning is one process area that has caused concerns related to structural damage. Although some contend that the process is better controlled lately, particularly when used with single-wafer setups, others say that there is still much that is not understood about megasonics.

"People have told us, in their wet benches, some people just basically don't use their megasonics anymore where they have patterned wafers," Butterbaugh said. But that's not an ideal situation either, of course, since they're just trading pattern damage in for higher defect levels.

"Right now, megasonics is not very controllable with any of the solutions that people have today," Marks said. Instead, Lam is focusing on alternative jet spray technology, as well as a new technology that it has been working on but is not yet ready to reveal. "We think we understand the fundamentals about why [megasonics] causes damage and why you can't control it in a way that is good for the trade-off of particle removal and damage. And we have some ideas about new solutions to the application of the megasonics that might overcome those problems, but it will be a while before we realize whether that's true or not."

Akrion offers megasonics capabilities in both its batch and single-wafer platforms, Kashkoush noted, but people have reported some damage associated with the megasonics, depending on how fragile or small the geometries are.

There are three key areas, according to Kashkoush, that need to be further explored to improve on megasonic capabilities: the frequency of the acoustic field, how the wave propagates into the sounds field, and evaluation of how the piezoelectric materials are manufactured. Megasonic frequency is in the 1 MHz range, he said, but Akrion and others have been looking into going to even higher frequencies, where the potential for damage gets smaller. The second area of wave propagation looks at diffusing the acoustic energy once it's in the liquid, including injecting a gas (e.g. nitrogen, argon or CO₂) into the liquid to lessen the sound intensity. "And I'm not sure if the industry has paid enough attention to the manufacturing of the crystals or the piezoelectric material," Kashkoush said.

3. Megasonic cleaning generated this damage to 0.25 µm aluminum. (Source: IMEC)

Detailed studies have revealed non-uniformity issues, as one example. And it's only been the past five years that this has become gradually recognized by the industry, and efforts have begun to further investigate megasonic cleaning. "It is very encouraging to see that the problem is now embraced by well-recognized basic physics research teams," he said, adding that, for the first time this year, the Acoustics conference in Paris included a special session dedicated to megasonic cleaning.